Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 0fcac2da authored by Ashish Kori's avatar Ashish Kori Committed by Gerrit - the friendly Code Review server
Browse files

spi: spi-msm-geni: Propagate SPI Slave MISO<->MOSI connection change 



Propagate Propagate following change from 4.14 to 5.4 for SPI driver.
'commit 005c3a05b41c3ea ("spi: spi-geni-qcom: Allow MISO<->MOSI
connectivity for slave pins")'.

Change-Id: I66ca5c2f851f8e3d1485580486cd2900a3756341
Signed-off-by: default avatarAshish Kori <akori@codeaurora.org>
parent 10386109

drivers/spi/spi-msm-geni.c

+10 −3
Original line number Diff line number Diff line
@@ -173,6 +173,7 @@ struct spi_geni_master { 
	bool disable_dma;

	bool slave_setup;

	bool slave_state;

	bool slave_cross_connected;

};



static void spi_slv_setup(struct spi_geni_master *mas);
@@ -207,8 +208,13 @@ static void spi_slv_setup(struct spi_geni_master *mas) 
{

	geni_write_reg(SPI_SLAVE_EN, mas->base, SE_SPI_SLAVE_EN);



	geni_write_reg(1, mas->base, GENI_OUTPUT_CTRL);



	if (mas->slave_cross_connected) {

		geni_write_reg(GENI_IO_MUX_1_EN, mas->base, GENI_OUTPUT_CTRL);

		geni_write_reg(IO1_SEL_TX | IO2_DATA_IN_SEL_PAD2 |

			IO3_DATA_IN_SEL_PAD2, mas->base, GENI_CFG_REG80);

	} else {

		geni_write_reg(GENI_IO_MUX_0_EN, mas->base, GENI_OUTPUT_CTRL);

	}

	geni_write_reg(START_TRIGGER, mas->base, SE_GENI_CFG_SEQ_START);

	/* ensure data is written to hardware register */

	wmb();
@@ -2042,7 +2048,8 @@ static int spi_geni_probe(struct platform_device *pdev) 
		spi->slave_abort = spi_slv_abort;

	}





	geni_mas->slave_cross_connected =

		of_property_read_bool(pdev->dev.of_node, "slv-cross-connected");

	spi->mode_bits = (SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH);

	spi->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);

	spi->num_chipselect = SPI_NUM_CHIPSELECT;

include/linux/msm-geni-se.h

+8 −0
Original line number Diff line number Diff line
@@ -96,6 +96,7 @@ struct se_geni_rsc { 
#define SE_GENI_CLK_SEL			(0x7C)

#define SE_GENI_CFG_SEQ_START		(0x84)

#define SE_GENI_CFG_REG			(0x200)

#define GENI_CFG_REG80			(0x240)

#define SE_GENI_BYTE_GRAN		(0x254)

#define SE_GENI_DMA_MODE_EN		(0x258)

#define SE_GENI_TX_PACKING_CFG0		(0x260)
@@ -134,6 +135,13 @@ struct se_geni_rsc { 


/* GENI_OUTPUT_CTRL fields */

#define DEFAULT_IO_OUTPUT_CTRL_MSK      (GENMASK(6, 0))

#define GENI_IO_MUX_0_EN		BIT(1)

#define GENI_IO_MUX_1_EN		BIT(2)



/* GENI_CFG_REG80 fields */

#define IO1_SEL_TX			BIT(2)

#define IO2_DATA_IN_SEL_PAD2		(GENMASK(11, 10))

#define IO3_DATA_IN_SEL_PAD2		BIT(15)



/* GENI_FORCE_DEFAULT_REG fields */

#define FORCE_DEFAULT	(BIT(0))