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Commit 0f895e4e authored by Maciej Purski's avatar Maciej Purski Committed by Krzysztof Kozlowski
Browse files

ARM: dts: exynos: Use labels instead of full paths in exynos4210-trats 



Extend camera and fimc nodes by labels, not by full path in Exynos
4210 Trats board.  This avoids error-prone redefinition of nodes.

Signed-off-by: default avatarMaciej Purski <m.purski@samsung.com>
Signed-off-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
parent e030be47

arch/arm/boot/dts/exynos4210-trats.dts

+37 −36
Original line number Diff line number Diff line
@@ -148,43 +148,12 @@ 
		};

	};



	camera {

		pinctrl-names = "default";

		pinctrl-0 = <>;

		status = "okay";



		fimc_0: fimc@11800000 {

			status = "okay";

			assigned-clocks = <&clock CLK_MOUT_FIMC0>,

					<&clock CLK_SCLK_FIMC0>;

			assigned-clock-parents = <&clock CLK_SCLK_MPLL>;

			assigned-clock-rates = <0>, <160000000>;

		};



		fimc_1: fimc@11810000 {

			status = "okay";

			assigned-clocks = <&clock CLK_MOUT_FIMC1>,

					<&clock CLK_SCLK_FIMC1>;

			assigned-clock-parents = <&clock CLK_SCLK_MPLL>;

			assigned-clock-rates = <0>, <160000000>;

};



		fimc_2: fimc@11820000 {

&camera {

	pinctrl-names = "default";

	pinctrl-0 = <>;

	status = "okay";

			assigned-clocks = <&clock CLK_MOUT_FIMC2>,

					<&clock CLK_SCLK_FIMC2>;

			assigned-clock-parents = <&clock CLK_SCLK_MPLL>;

			assigned-clock-rates = <0>, <160000000>;

		};



		fimc_3: fimc@11830000 {

			status = "okay";

			assigned-clocks = <&clock CLK_MOUT_FIMC3>,

					<&clock CLK_SCLK_FIMC3>;

			assigned-clock-parents = <&clock CLK_SCLK_MPLL>;

			assigned-clock-rates = <0>, <160000000>;

		};

	};

};



&cpu0 {
@@ -234,6 +203,38 @@ 
	vbus-supply = <&safe1_sreg>;

};



&fimc_0 {

	status = "okay";

	assigned-clocks = <&clock CLK_MOUT_FIMC0>,

			  <&clock CLK_SCLK_FIMC0>;

	assigned-clock-parents = <&clock CLK_SCLK_MPLL>;

	assigned-clock-rates = <0>, <160000000>;

};



&fimc_1 {

	status = "okay";

	assigned-clocks = <&clock CLK_MOUT_FIMC1>,

			  <&clock CLK_SCLK_FIMC1>;

	assigned-clock-parents = <&clock CLK_SCLK_MPLL>;

	assigned-clock-rates = <0>, <160000000>;

};



&fimc_2 {

	status = "okay";

	assigned-clocks = <&clock CLK_MOUT_FIMC2>,

			  <&clock CLK_SCLK_FIMC2>;

	assigned-clock-parents = <&clock CLK_SCLK_MPLL>;

		assigned-clock-rates = <0>, <160000000>;

};



&fimc_3 {

	status = "okay";

	assigned-clocks = <&clock CLK_MOUT_FIMC3>,

			  <&clock CLK_SCLK_FIMC3>;

	assigned-clock-parents = <&clock CLK_SCLK_MPLL>;

	assigned-clock-rates = <0>, <160000000>;

};



&fimd {

	status = "okay";

};