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Commit 0f3a7459 authored by John Youn's avatar John Youn Committed by Felipe Balbi
Browse files

usb: dwc2: Remove unused otg_ver parameter 



The otg_ver parameter only controls the SRP pulsing method and defaults
to the 1.3 behavior. It is unused and can be removed.

Signed-off-by: default avatarJohn Youn <johnyoun@synopsys.com>
Signed-off-by: default avatarFelipe Balbi <felipe.balbi@linux.intel.com>
parent 749494b6

drivers/usb/dwc2/core.c

+0 −5
Original line number Diff line number Diff line
@@ -751,11 +751,6 @@ bool dwc2_force_mode_if_needed(struct dwc2_hsotg *hsotg, bool host) 
	return dwc2_force_mode(hsotg, host);

}



u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg)

{

	return hsotg->params.otg_ver == 1 ? 0x0200 : 0x0103;

}



bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg)

{

	if (dwc2_readl(hsotg->regs + GSNPSID) == 0xffffffff)

drivers/usb/dwc2/core.h

+0 −9
Original line number Diff line number Diff line
@@ -298,9 +298,6 @@ enum dwc2_ep0_state { 
 *                       1 - SRP Only capable

 *                       2 - No HNP/SRP capable (always available)

 *                      Defaults to best available option (0, 1, then 2)

 * @otg_ver:            OTG version supported

 *                       0 - 1.3 (default)

 *                       1 - 2.0

 * @host_dma:           Specifies whether to use slave or DMA mode for accessing

 *                      the data FIFOs. The driver will automatically detect the

 *                      value for this parameter if none is specified.
@@ -464,7 +461,6 @@ struct dwc2_core_params { 
#define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE		1

#define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE	2



	int otg_ver;

	int dma_desc_enable;

	int dma_desc_fs_enable;

	int speed;
@@ -1175,11 +1171,6 @@ void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); 
void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg);

void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg);



/*

 * Return OTG version - either 1.3 or 2.0

 */

u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg);



/* Gadget defines */

#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \

	IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)

drivers/usb/dwc2/hcd.c

+0 −3
Original line number Diff line number Diff line
@@ -2260,10 +2260,7 @@ static int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup) 
	/* Program the GOTGCTL register */

	otgctl = dwc2_readl(hsotg->regs + GOTGCTL);

	otgctl &= ~GOTGCTL_OTGVER;

	if (hsotg->params.otg_ver > 0)

		otgctl |= GOTGCTL_OTGVER;

	dwc2_writel(otgctl, hsotg->regs + GOTGCTL);

	dev_dbg(hsotg->dev, "OTG VER PARAM: %d\n", hsotg->params.otg_ver);



	/* Clear the SRP success bit for FS-I2c */

	hsotg->srp_success = 0;

drivers/usb/dwc2/params.c

+0 −23
Original line number Diff line number Diff line
@@ -40,7 +40,6 @@ 


static const struct dwc2_core_params params_hi6220 = {

	.otg_cap			= 2,	/* No HNP/SRP capable */

	.otg_ver			= 0,	/* 1.3 */

	.dma_desc_enable		= 0,

	.dma_desc_fs_enable		= 0,

	.speed				= 0,	/* High Speed */
@@ -71,7 +70,6 @@ static const struct dwc2_core_params params_hi6220 = { 


static const struct dwc2_core_params params_bcm2835 = {

	.otg_cap			= 0,	/* HNP/SRP capable */

	.otg_ver			= 0,	/* 1.3 */

	.dma_desc_enable		= 0,

	.dma_desc_fs_enable		= 0,

	.speed				= 0,	/* High Speed */
@@ -101,7 +99,6 @@ static const struct dwc2_core_params params_bcm2835 = { 


static const struct dwc2_core_params params_rk3066 = {

	.otg_cap			= 2,	/* non-HNP/non-SRP */

	.otg_ver			= -1,

	.dma_desc_enable		= 0,

	.dma_desc_fs_enable		= 0,

	.speed				= -1,
@@ -132,7 +129,6 @@ static const struct dwc2_core_params params_rk3066 = { 


static const struct dwc2_core_params params_ltq = {

	.otg_cap			= 2,	/* non-HNP/non-SRP */

	.otg_ver			= -1,

	.dma_desc_enable		= -1,

	.dma_desc_fs_enable		= -1,

	.speed				= -1,
@@ -163,7 +159,6 @@ static const struct dwc2_core_params params_ltq = { 


static const struct dwc2_core_params params_amlogic = {

	.otg_cap			= DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE,

	.otg_ver			= -1,

	.dma_desc_enable		= 0,

	.dma_desc_fs_enable		= 0,

	.speed				= DWC2_SPEED_PARAM_HIGH,
@@ -194,7 +189,6 @@ static const struct dwc2_core_params params_amlogic = { 


static const struct dwc2_core_params params_default = {

	.otg_cap			= -1,

	.otg_ver			= -1,



	/*

	 * Disable descriptor dma mode by default as the HW can support
@@ -978,22 +972,6 @@ static void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val) 
						GAHBCFG_HBSTLEN_SHIFT;

}



static void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val)

{

	if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {

		if (val >= 0) {

			dev_err(hsotg->dev,

				"'%d' invalid for parameter otg_ver\n", val);

			dev_err(hsotg->dev,

				"otg_ver must be 0 (for OTG 1.3 support) or 1 (for OTG 2.0 support)\n");

		}

		val = 0;

		dev_dbg(hsotg->dev, "Setting otg_ver to %d\n", val);

	}



	hsotg->params.otg_ver = val;

}



static void dwc2_set_param_uframe_sched(struct dwc2_hsotg *hsotg, int val)

{

	if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
@@ -1154,7 +1132,6 @@ static void dwc2_set_parameters(struct dwc2_hsotg *hsotg, 
			params->en_multiple_tx_fifo);

	dwc2_set_param_reload_ctl(hsotg, params->reload_ctl);

	dwc2_set_param_ahbcfg(hsotg, params->ahbcfg);

	dwc2_set_param_otg_ver(hsotg, params->otg_ver);

	dwc2_set_param_uframe_sched(hsotg, params->uframe_sched);

	dwc2_set_param_external_id_pin_ctl(hsotg, params->external_id_pin_ctl);

	dwc2_set_param_hibernation(hsotg, params->hibernation);