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Commit 0f0af0a5 authored by Odelu Kukatla's avatar Odelu Kukatla
Browse files

ARM: dts: msm: Add handles for PCIE clocks 

PCIE cocks need to be enabled for QoS settings programming,
so add PCIE clock handles.

Change-Id: I882f07b33b3e7ffaaabeaca258831b8ac0757973
parent ea572074

qcom/shima-pcie.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -59,7 +59,7 @@ 
			RPMH_REGULATOR_LEVEL_NOM 100000000>; /* Gen3 */



		interconnect-names = "icc_path";

		interconnects = <&aggre2_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;

		interconnects = <&aggre1_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;



		clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,

			<&rpmhcc RPMH_CXO_CLK>,

qcom/shima.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -2052,7 +2052,9 @@ 
		#interconnect-cells = <1>;

		qcom,bcm-voter-names = "hlos";

		qcom,bcm-voters = <&apps_bcm_voter>;

		clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,

		clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,

			<&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,

			<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,

			<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;

	};
@@ -2062,9 +2064,7 @@ 
		#interconnect-cells = <1>;

		qcom,bcm-voter-names = "hlos";

		qcom,bcm-voters = <&apps_bcm_voter>;

		clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,

			<&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,

			<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,

		clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,

			<&rpmhcc RPMH_IPA_CLK>;

	};