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Commit 0e79284d authored by Ben Widawsky's avatar Ben Widawsky Committed by Daniel Vetter
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drm/i915: Reorder/respace MI instruction definition 



A few command were out of numerical order and had different spacing. Put
them back in numerical order, with proper spacing.

Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 5382f5f3

drivers/gpu/drm/i915/i915_reg.h

+26 −26
Original line number Original line Diff line number Diff line
@@ -193,10 +193,13 @@ 
#define   MI_SCENE_COUNT	(1 << 3) /* just increment scene count */

#define   MI_SCENE_COUNT	(1 << 3) /* just increment scene count */

#define   MI_END_SCENE		(1 << 4) /* flush binner and incr scene count */

#define   MI_END_SCENE		(1 << 4) /* flush binner and incr scene count */

#define   MI_INVALIDATE_ISP	(1 << 5) /* invalidate indirect state pointers */

#define   MI_INVALIDATE_ISP	(1 << 5) /* invalidate indirect state pointers */

#define MI_REPORT_HEAD		MI_INSTR(0x07, 0)

#define MI_ARB_ON_OFF		MI_INSTR(0x08, 0)

#define   MI_ARB_ENABLE			(1<<0)

#define   MI_ARB_DISABLE		(0<<0)

#define MI_BATCH_BUFFER_END	MI_INSTR(0x0a, 0)

#define MI_BATCH_BUFFER_END	MI_INSTR(0x0a, 0)

#define MI_SUSPEND_FLUSH	MI_INSTR(0x0b, 0)

#define MI_SUSPEND_FLUSH	MI_INSTR(0x0b, 0)

#define   MI_SUSPEND_FLUSH_EN	(1<<0)

#define   MI_SUSPEND_FLUSH_EN	(1<<0)

#define MI_REPORT_HEAD		MI_INSTR(0x07, 0)

#define MI_OVERLAY_FLIP		MI_INSTR(0x11, 0)

#define MI_OVERLAY_FLIP		MI_INSTR(0x11, 0)

#define   MI_OVERLAY_CONTINUE	(0x0<<21)

#define   MI_OVERLAY_CONTINUE	(0x0<<21)

#define   MI_OVERLAY_ON		(0x1<<21)

#define   MI_OVERLAY_ON		(0x1<<21)
@@ -212,10 +215,24 @@ 
#define   MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)

#define   MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)

#define   MI_DISPLAY_FLIP_IVB_PLANE_C  (4 << 19)

#define   MI_DISPLAY_FLIP_IVB_PLANE_C  (4 << 19)

#define   MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)

#define   MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)

#define MI_ARB_ON_OFF		MI_INSTR(0x08, 0)

#define MI_SEMAPHORE_MBOX	MI_INSTR(0x16, 1) /* gen6+ */

#define   MI_ARB_ENABLE			(1<<0)

#define   MI_SEMAPHORE_GLOBAL_GTT    (1<<22)

#define   MI_ARB_DISABLE		(0<<0)

#define   MI_SEMAPHORE_UPDATE	    (1<<21)



#define   MI_SEMAPHORE_COMPARE	    (1<<20)

#define   MI_SEMAPHORE_REGISTER	    (1<<18)

#define   MI_SEMAPHORE_SYNC_VR	    (0<<16) /* RCS  wait for VCS  (RVSYNC) */

#define   MI_SEMAPHORE_SYNC_VER	    (1<<16) /* RCS  wait for VECS (RVESYNC) */

#define   MI_SEMAPHORE_SYNC_BR	    (2<<16) /* RCS  wait for BCS  (RBSYNC) */

#define   MI_SEMAPHORE_SYNC_BV	    (0<<16) /* VCS  wait for BCS  (VBSYNC) */

#define   MI_SEMAPHORE_SYNC_VEV	    (1<<16) /* VCS  wait for VECS (VVESYNC) */

#define   MI_SEMAPHORE_SYNC_RV	    (2<<16) /* VCS  wait for RCS  (VRSYNC) */

#define   MI_SEMAPHORE_SYNC_RB	    (0<<16) /* BCS  wait for RCS  (BRSYNC) */

#define   MI_SEMAPHORE_SYNC_VEB	    (1<<16) /* BCS  wait for VECS (BVESYNC) */

#define   MI_SEMAPHORE_SYNC_VB	    (2<<16) /* BCS  wait for VCS  (BVSYNC) */

#define   MI_SEMAPHORE_SYNC_BVE	    (0<<16) /* VECS wait for BCS  (VEBSYNC) */

#define   MI_SEMAPHORE_SYNC_VVE	    (1<<16) /* VECS wait for VCS  (VEVSYNC) */

#define   MI_SEMAPHORE_SYNC_RVE	    (2<<16) /* VECS wait for RCS  (VERSYNC) */

#define   MI_SEMAPHORE_SYNC_INVALID  (3<<16)

#define MI_SET_CONTEXT		MI_INSTR(0x18, 0)

#define MI_SET_CONTEXT		MI_INSTR(0x18, 0)

#define   MI_MM_SPACE_GTT		(1<<8)

#define   MI_MM_SPACE_GTT		(1<<8)

#define   MI_MM_SPACE_PHYSICAL		(0<<8)

#define   MI_MM_SPACE_PHYSICAL		(0<<8)
@@ -252,24 +269,7 @@ 
#define MI_BATCH_BUFFER_START	MI_INSTR(0x31, 0)

#define MI_BATCH_BUFFER_START	MI_INSTR(0x31, 0)

#define   MI_BATCH_GTT		    (2<<6) /* aliased with (1<<7) on gen4 */

#define   MI_BATCH_GTT		    (2<<6) /* aliased with (1<<7) on gen4 */

#define MI_BATCH_BUFFER_START_GEN8	MI_INSTR(0x31, 1)

#define MI_BATCH_BUFFER_START_GEN8	MI_INSTR(0x31, 1)

#define MI_SEMAPHORE_MBOX	MI_INSTR(0x16, 1) /* gen6+ */



#define  MI_SEMAPHORE_GLOBAL_GTT    (1<<22)

#define  MI_SEMAPHORE_UPDATE	    (1<<21)

#define  MI_SEMAPHORE_COMPARE	    (1<<20)

#define  MI_SEMAPHORE_REGISTER	    (1<<18)

#define  MI_SEMAPHORE_SYNC_VR	    (0<<16) /* RCS  wait for VCS  (RVSYNC) */

#define  MI_SEMAPHORE_SYNC_VER	    (1<<16) /* RCS  wait for VECS (RVESYNC) */

#define  MI_SEMAPHORE_SYNC_BR	    (2<<16) /* RCS  wait for BCS  (RBSYNC) */

#define  MI_SEMAPHORE_SYNC_BV	    (0<<16) /* VCS  wait for BCS  (VBSYNC) */

#define  MI_SEMAPHORE_SYNC_VEV	    (1<<16) /* VCS  wait for VECS (VVESYNC) */

#define  MI_SEMAPHORE_SYNC_RV	    (2<<16) /* VCS  wait for RCS  (VRSYNC) */

#define  MI_SEMAPHORE_SYNC_RB	    (0<<16) /* BCS  wait for RCS  (BRSYNC) */

#define  MI_SEMAPHORE_SYNC_VEB	    (1<<16) /* BCS  wait for VECS (BVESYNC) */

#define  MI_SEMAPHORE_SYNC_VB	    (2<<16) /* BCS  wait for VCS  (BVSYNC) */

#define  MI_SEMAPHORE_SYNC_BVE	    (0<<16) /* VECS wait for BCS  (VEBSYNC) */

#define  MI_SEMAPHORE_SYNC_VVE	    (1<<16) /* VECS wait for VCS  (VEVSYNC) */

#define  MI_SEMAPHORE_SYNC_RVE	    (2<<16) /* VECS wait for RCS  (VERSYNC) */

#define  MI_SEMAPHORE_SYNC_INVALID  (3<<16)





#define MI_PREDICATE_RESULT_2	(0x2214)

#define MI_PREDICATE_RESULT_2	(0x2214)

#define  LOWER_SLICE_ENABLED	(1<<0)

#define  LOWER_SLICE_ENABLED	(1<<0)