Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 0e7488ed authored by Ezequiel Garcia's avatar Ezequiel Garcia Committed by Vinod Koul
Browse files

dma: mv_xor: Remove all interrupt magic numbers 



This commit replaces the current magic numbers in the interrupt handling
with proper macros, which makes more readable and self-documenting.

While here replace the BUG() with a noisy WARN_ON(). There's no reason
to tear down the entire system for an DMA IRQ error.

Signed-off-by: default avatarEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: default avatarVinod Koul <vinod.koul@intel.com>
parent dfc97661

drivers/dma/mv_xor.c

+9 −19
Original line number Diff line number Diff line
@@ -50,9 +50,9 @@ static void mv_desc_init(struct mv_xor_desc_slot *desc, 
{

	struct mv_xor_desc *hw_desc = desc->hw_desc;



	hw_desc->status = (1 << 31);

	hw_desc->status = XOR_DESC_DMA_OWNED;

	hw_desc->phy_next_desc = 0;

	hw_desc->desc_command = (1 << 31);

	hw_desc->desc_command = XOR_DESC_EOD_INT_EN;

	hw_desc->phy_dest_addr = addr;

	hw_desc->byte_count = byte_count;

}
@@ -105,17 +105,9 @@ static u32 mv_chan_get_intr_cause(struct mv_xor_chan *chan) 
	return intr_cause;

}



static int mv_is_err_intr(u32 intr_cause)

{

	if (intr_cause & ((1<<4)|(1<<5)|(1<<6)|(1<<7)|(1<<8)|(1<<9)))

		return 1;



	return 0;

}



static void mv_xor_device_clear_eoc_cause(struct mv_xor_chan *chan)

{

	u32 val = ~(1 << (chan->idx * 16));

	u32 val = ~(XOR_INT_END_OF_DESC	<< (chan->idx * 16));

	dev_dbg(mv_chan_to_devp(chan), "%s, val 0x%08x\n", __func__, val);

	writel_relaxed(val, XOR_INTR_CAUSE(chan));

}
@@ -627,18 +619,16 @@ static void mv_dump_xor_regs(struct mv_xor_chan *chan) 
static void mv_xor_err_interrupt_handler(struct mv_xor_chan *chan,

					 u32 intr_cause)

{

	if (intr_cause & (1 << 4)) {

	     dev_dbg(mv_chan_to_devp(chan),

		     "ignore this error\n");

	if (intr_cause & XOR_INT_ERR_DECODE) {

		dev_dbg(mv_chan_to_devp(chan), "ignoring address decode error\n");

		return;

	}



	dev_err(mv_chan_to_devp(chan),

		"error on chan %d. intr cause 0x%08x\n",

	dev_err(mv_chan_to_devp(chan), "error on chan %d. intr cause 0x%08x\n",

		chan->idx, intr_cause);



	mv_dump_xor_regs(chan);

	BUG();

	WARN_ON(1);

}



static irqreturn_t mv_xor_interrupt_handler(int irq, void *data)
@@ -648,7 +638,7 @@ static irqreturn_t mv_xor_interrupt_handler(int irq, void *data) 


	dev_dbg(mv_chan_to_devp(chan), "intr cause %x\n", intr_cause);



	if (mv_is_err_intr(intr_cause))

	if (intr_cause & XOR_INTR_ERRORS)

		mv_xor_err_interrupt_handler(chan, intr_cause);



	tasklet_schedule(&chan->irq_tasklet);

drivers/dma/mv_xor.h

+21 −1
Original line number Diff line number Diff line
@@ -34,6 +34,9 @@ 
#define XOR_OPERATION_MODE_MEMCPY	2

#define XOR_DESCRIPTOR_SWAP		BIT(14)



#define XOR_DESC_DMA_OWNED		BIT(31)

#define XOR_DESC_EOD_INT_EN		BIT(31)



#define XOR_CURR_DESC(chan)	(chan->mmr_high_base + 0x10 + (chan->idx * 4))

#define XOR_NEXT_DESC(chan)	(chan->mmr_high_base + 0x00 + (chan->idx * 4))

#define XOR_BYTE_COUNT(chan)	(chan->mmr_high_base + 0x20 + (chan->idx * 4))
@@ -48,7 +51,24 @@ 
#define XOR_INTR_MASK(chan)	(chan->mmr_base + 0x40)

#define XOR_ERROR_CAUSE(chan)	(chan->mmr_base + 0x50)

#define XOR_ERROR_ADDR(chan)	(chan->mmr_base + 0x60)

#define XOR_INTR_MASK_VALUE	0x3F5



#define XOR_INT_END_OF_DESC	BIT(0)

#define XOR_INT_END_OF_CHAIN	BIT(1)

#define XOR_INT_STOPPED		BIT(2)

#define XOR_INT_PAUSED		BIT(3)

#define XOR_INT_ERR_DECODE	BIT(4)

#define XOR_INT_ERR_RDPROT	BIT(5)

#define XOR_INT_ERR_WRPROT	BIT(6)

#define XOR_INT_ERR_OWN		BIT(7)

#define XOR_INT_ERR_PAR		BIT(8)

#define XOR_INT_ERR_MBUS	BIT(9)



#define XOR_INTR_ERRORS		(XOR_INT_ERR_DECODE | XOR_INT_ERR_RDPROT | \

				 XOR_INT_ERR_WRPROT | XOR_INT_ERR_OWN    | \

				 XOR_INT_ERR_PAR    | XOR_INT_ERR_MBUS)



#define XOR_INTR_MASK_VALUE	(XOR_INT_END_OF_DESC | \

				 XOR_INT_STOPPED     | XOR_INTR_ERRORS)



#define WINDOW_BASE(w)		(0x50 + ((w) << 2))

#define WINDOW_SIZE(w)		(0x70 + ((w) << 2))