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Commit 0e63665a authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mtd/fixes-for-5.2-final' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux 

Pull mtf fixes from Miquel Raynal:

 - Fix the memory organization structure of a Macronix SPI-NAND chip.

 - Fix a build dependency wrongly described.

 - Fix the sunxi NAND driver for A23/A33 SoCs by (a) reverting the
   faulty commit introducing broken DMA support and (b) applying another
   commit bringing working DMA support.

* tag 'mtd/fixes-for-5.2-final' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux:
  mtd: rawnand: sunxi: Add A23/A33 DMA support with extra MBUS configuration
  Revert "mtd: rawnand: sunxi: Add A23/A33 DMA support"
  mtd: rawnand: ingenic: Fix ingenic_ecc dependency
  mtd: spinand: Fix max_bad_eraseblocks_per_lun info in memorg
parents 881ed91f c7a87ceb

drivers/mtd/nand/raw/ingenic/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -16,7 +16,7 @@ config MTD_NAND_JZ4780 
if MTD_NAND_JZ4780



config MTD_NAND_INGENIC_ECC

	tristate

	bool



config MTD_NAND_JZ4740_ECC

	tristate "Hardware BCH support for JZ4740 SoC"

drivers/mtd/nand/raw/ingenic/Makefile

+3 −1
Original line number Diff line number Diff line
@@ -2,7 +2,9 @@ 
obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o

obj-$(CONFIG_MTD_NAND_JZ4780) += ingenic_nand.o



obj-$(CONFIG_MTD_NAND_INGENIC_ECC) += ingenic_ecc.o

ingenic_nand-y += ingenic_nand_drv.o

ingenic_nand-$(CONFIG_MTD_NAND_INGENIC_ECC) += ingenic_ecc.o



obj-$(CONFIG_MTD_NAND_JZ4740_ECC) += jz4740_ecc.o

obj-$(CONFIG_MTD_NAND_JZ4725B_BCH) += jz4725b_bch.o

obj-$(CONFIG_MTD_NAND_JZ4780_BCH) += jz4780_bch.o

drivers/mtd/nand/raw/ingenic/ingenic_ecc.c

+0 −9
Original line number Diff line number Diff line
@@ -30,7 +30,6 @@ int ingenic_ecc_calculate(struct ingenic_ecc *ecc, 
{

	return ecc->ops->calculate(ecc, params, buf, ecc_code);

}

EXPORT_SYMBOL(ingenic_ecc_calculate);



/**

 * ingenic_ecc_correct() - detect and correct bit errors
@@ -51,7 +50,6 @@ int ingenic_ecc_correct(struct ingenic_ecc *ecc, 
{

	return ecc->ops->correct(ecc, params, buf, ecc_code);

}

EXPORT_SYMBOL(ingenic_ecc_correct);



/**

 * ingenic_ecc_get() - get the ECC controller device
@@ -111,7 +109,6 @@ struct ingenic_ecc *of_ingenic_ecc_get(struct device_node *of_node) 
	}

	return ecc;

}

EXPORT_SYMBOL(of_ingenic_ecc_get);



/**

 * ingenic_ecc_release() - release the ECC controller device
@@ -122,7 +119,6 @@ void ingenic_ecc_release(struct ingenic_ecc *ecc) 
	clk_disable_unprepare(ecc->clk);

	put_device(ecc->dev);

}

EXPORT_SYMBOL(ingenic_ecc_release);



int ingenic_ecc_probe(struct platform_device *pdev)

{
@@ -159,8 +155,3 @@ int ingenic_ecc_probe(struct platform_device *pdev) 
	return 0;

}

EXPORT_SYMBOL(ingenic_ecc_probe);
 


MODULE_AUTHOR("Alex Smith <alex@alex-smith.me.uk>");

MODULE_AUTHOR("Harvey Hunt <harveyhuntnexus@gmail.com>");

MODULE_DESCRIPTION("Ingenic ECC common driver");

MODULE_LICENSE("GPL v2");

drivers/mtd/nand/raw/sunxi_nand.c

+15 −25
Original line number Diff line number Diff line
@@ -51,6 +51,7 @@ 
#define NFC_REG_USER_DATA(x)	(0x0050 + ((x) * 4))

#define NFC_REG_SPARE_AREA	0x00A0

#define NFC_REG_PAT_ID		0x00A4

#define NFC_REG_MDMA_CNT	0x00C4

#define NFC_RAM0_BASE		0x0400

#define NFC_RAM1_BASE		0x0800
@@ -69,6 +70,7 @@ 
#define NFC_PAGE_SHIFT(x)	(((x) < 10 ? 0 : (x) - 10) << 8)

#define NFC_SAM			BIT(12)

#define NFC_RAM_METHOD		BIT(14)

#define NFC_DMA_TYPE_NORMAL	BIT(15)

#define NFC_DEBUG_CTL		BIT(31)



/* define bit use in NFC_ST */
@@ -205,14 +207,13 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand) 
 * NAND Controller capabilities structure: stores NAND controller capabilities

 * for distinction between compatible strings.

 *

 * @sram_through_ahb:	On A23, we choose to access the internal RAM through AHB

 *                      instead of MBUS (less configuration). A10, A10s, A13 and

 *                      A20 use the MBUS but no extra configuration is needed.

 * @extra_mbus_conf:	Contrary to A10, A10s and A13, accessing internal RAM

 *			through MBUS on A23/A33 needs extra configuration.

 * @reg_io_data:	I/O data register

 * @dma_maxburst:	DMA maxburst

 */

struct sunxi_nfc_caps {

	bool sram_through_ahb;

	bool extra_mbus_conf;

	unsigned int reg_io_data;

	unsigned int dma_maxburst;

};
@@ -368,28 +369,12 @@ static int sunxi_nfc_dma_op_prepare(struct sunxi_nfc *nfc, const void *buf, 
		goto err_unmap_buf;

	}



	/*

	 * On A23, we suppose the "internal RAM" (p.12 of the NFC user manual)

	 * refers to the NAND controller's internal SRAM. This memory is mapped

	 * and so is accessible from the AHB. It seems that it can also be

	 * accessed by the MBUS. MBUS accesses are mandatory when using the

	 * internal DMA instead of the external DMA engine.

	 *

	 * During DMA I/O operation, either we access this memory from the AHB

	 * by clearing the NFC_RAM_METHOD bit, or we set the bit and use the

	 * MBUS. In this case, we should also configure the MBUS DMA length

	 * NFC_REG_MDMA_CNT(0xC4) to be chunksize * nchunks. NAND I/O over MBUS

	 * are also limited to 32kiB pages.

	 */

	if (nfc->caps->sram_through_ahb)

		writel(readl(nfc->regs + NFC_REG_CTL) & ~NFC_RAM_METHOD,

		       nfc->regs + NFC_REG_CTL);

	else

	writel(readl(nfc->regs + NFC_REG_CTL) | NFC_RAM_METHOD,

	       nfc->regs + NFC_REG_CTL);



	writel(nchunks, nfc->regs + NFC_REG_SECTOR_NUM);

	writel(chunksize, nfc->regs + NFC_REG_CNT);

	if (nfc->caps->extra_mbus_conf)

		writel(chunksize * nchunks, nfc->regs + NFC_REG_MDMA_CNT);



	dmat = dmaengine_submit(dmad);
@@ -2151,6 +2136,11 @@ static int sunxi_nfc_probe(struct platform_device *pdev) 
		dmac_cfg.src_maxburst = nfc->caps->dma_maxburst;

		dmac_cfg.dst_maxburst = nfc->caps->dma_maxburst;

		dmaengine_slave_config(nfc->dmac, &dmac_cfg);



		if (nfc->caps->extra_mbus_conf)

			writel(readl(nfc->regs + NFC_REG_CTL) |

			       NFC_DMA_TYPE_NORMAL, nfc->regs + NFC_REG_CTL);



	} else {

		dev_warn(dev, "failed to request rxtx DMA channel\n");

	}
@@ -2200,7 +2190,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_a10_caps = { 
};



static const struct sunxi_nfc_caps sunxi_nfc_a23_caps = {

	.sram_through_ahb = true,

	.extra_mbus_conf = true,

	.reg_io_data = NFC_REG_A23_IO_DATA,

	.dma_maxburst = 8,

};