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Commit 0e390a33 authored by Mika Kahola's avatar Mika Kahola Committed by Jani Nikula
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drm/i915: Read DP branch device HW revision 



HW revision is mandatory field for DisplayPort branch
devices. This is defined in DPCD register field 0x509.

v2: move drm_dp_ds_revision structure to be part of
    drm_dp_link structure (Daniel)
v3: remove dependency to drm_dp_helper but instead parse
    DPCD and print HW revision info to dmesg (Ville)

Reviewed-by: default avatarJim Bride <jim.bride@linux.intel.com>
Signed-off-by: default avatarMika Kahola <mika.kahola@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1473419458-17080-8-git-send-email-mika.kahola@intel.com
parent b6339585

drivers/gpu/drm/i915/intel_dp.c

+21 −0
Original line number Diff line number Diff line
@@ -1419,6 +1419,25 @@ static void intel_dp_print_rates(struct intel_dp *intel_dp) 
	DRM_DEBUG_KMS("common rates: %s\n", str);

}



static void intel_dp_print_hw_revision(struct intel_dp *intel_dp)

{

	uint8_t rev;

	int len;



	if ((drm_debug & DRM_UT_KMS) == 0)

		return;



	if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &

	      DP_DWN_STRM_PORT_PRESENT))

		return;



	len = drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_HW_REV, &rev, 1);

	if (len < 0)

		return;



	DRM_DEBUG_KMS("sink hw revision: %d.%d\n", (rev & 0xf0) >> 4, rev & 0xf);

}



static int rate_to_index(int find, const int *rates)

{

	int i = 0;
@@ -4312,6 +4331,8 @@ intel_dp_long_pulse(struct intel_connector *intel_connector) 


	intel_dp_probe_oui(intel_dp);



	intel_dp_print_hw_revision(intel_dp);



	intel_dp_configure_mst(intel_dp);



	if (intel_dp->is_mst) {

include/drm/drm_dp_helper.h

+1 −0
Original line number Diff line number Diff line
@@ -446,6 +446,7 @@ 
#define DP_SINK_OUI			    0x400

#define DP_BRANCH_OUI			    0x500

#define DP_BRANCH_ID                        0x503

#define DP_BRANCH_HW_REV                    0x509



#define DP_SET_POWER                        0x600

# define DP_SET_POWER_D0                    0x1