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Commit 0e21e3b0 authored by Philippe CORNU's avatar Philippe CORNU Committed by Benjamin Gaignard
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drm/stm: ltdc: Lindent and minor cleanups 



Lindent then checkpatch --strict cleanups

Signed-off-by: default avatarPhilippe CORNU <philippe.cornu@st.com>
Reviewed-by: default avatarBenjamin Gaignard <benjamin.gaignard@linaro.org>
Signed-off-by: default avatarBenjamin Gaignard <benjamin.gaignard@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/1500552357-29487-4-git-send-email-philippe.cornu@st.com
parent 444d0db5

drivers/gpu/drm/stm/ltdc.c

+85 −87
Original line number Diff line number Diff line
@@ -42,7 +42,7 @@ 
 * an extra offset specified with reg_ofs.

 */

#define REG_OFS_NONE	0

#define REG_OFS_4	4 /* Insertion of "Layer Configuration 2" reg */

#define REG_OFS_4	4		/* Insertion of "Layer Conf. 2" reg */

#define REG_OFS		(ldev->caps.reg_ofs)

#define LAY_OFS		0x80		/* Register Offset between 2 layers */
@@ -62,32 +62,32 @@ 
#define LTDC_IER	0x0034		/* Interrupt Enable */

#define LTDC_ISR	0x0038		/* Interrupt Status */

#define LTDC_ICR	0x003C		/* Interrupt Clear */

#define LTDC_LIPCR	0x0040 /* Line Interrupt Position Configuration */

#define LTDC_LIPCR	0x0040		/* Line Interrupt Position Conf. */

#define LTDC_CPSR	0x0044		/* Current Position Status */

#define LTDC_CDSR	0x0048		/* Current Display Status */



/* Layer register offsets */

#define LTDC_L1LC1R	(0x0080)	   /* L1 Layer Configuration 1 */

#define LTDC_L1LC2R	(0x0084)	   /* L1 Layer Configuration 2 */

#define LTDC_L1CR	(0x0084 + REG_OFS) /* L1 Control */

#define LTDC_L1WHPCR	(0x0088 + REG_OFS) /* L1 Window Hor Position Config */

#define LTDC_L1WVPCR	(0x008C + REG_OFS) /* L1 Window Vert Position Config */

#define LTDC_L1CKCR	(0x0090 + REG_OFS) /* L1 Color Keying Configuration */

#define LTDC_L1PFCR	(0x0094 + REG_OFS) /* L1 Pixel Format Configuration */

#define LTDC_L1CACR	(0x0098 + REG_OFS) /* L1 Constant Alpha Config */

#define LTDC_L1DCCR	(0x009C + REG_OFS) /* L1 Default Color Configuration */

#define LTDC_L1BFCR	(0x00A0 + REG_OFS) /* L1 Blend Factors Configuration */

#define LTDC_L1FBBCR	(0x00A4 + REG_OFS) /* L1 FrameBuffer Bus Control */

#define LTDC_L1AFBCR	(0x00A8 + REG_OFS) /* L1 AuxFB Control */

#define LTDC_L1CFBAR	(0x00AC + REG_OFS) /* L1 Color FrameBuffer Address */

#define LTDC_L1CFBLR	(0x00B0 + REG_OFS) /* L1 Color FrameBuffer Length */

#define LTDC_L1CFBLNR	(0x00B4 + REG_OFS) /* L1 Color FrameBuffer Line Nb */

#define LTDC_L1AFBAR	(0x00B8 + REG_OFS) /* L1 AuxFB Address */

#define LTDC_L1AFBLR	(0x00BC + REG_OFS) /* L1 AuxFB Length */

#define LTDC_L1AFBLNR	(0x00C0 + REG_OFS) /* L1 AuxFB Line Number */

#define LTDC_L1CLUTWR	(0x00C4 + REG_OFS) /* L1 CLUT Write */

#define LTDC_L1YS1R	(0x00E0 + REG_OFS) /* L1 YCbCr Scale 1 */

#define LTDC_L1YS2R	(0x00E4 + REG_OFS) /* L1 YCbCr Scale 2 */

#define LTDC_L1LC1R	(0x80)		/* L1 Layer Configuration 1 */

#define LTDC_L1LC2R	(0x84)		/* L1 Layer Configuration 2 */

#define LTDC_L1CR	(0x84 + REG_OFS)/* L1 Control */

#define LTDC_L1WHPCR	(0x88 + REG_OFS)/* L1 Window Hor Position Config */

#define LTDC_L1WVPCR	(0x8C + REG_OFS)/* L1 Window Vert Position Config */

#define LTDC_L1CKCR	(0x90 + REG_OFS)/* L1 Color Keying Configuration */

#define LTDC_L1PFCR	(0x94 + REG_OFS)/* L1 Pixel Format Configuration */

#define LTDC_L1CACR	(0x98 + REG_OFS)/* L1 Constant Alpha Config */

#define LTDC_L1DCCR	(0x9C + REG_OFS)/* L1 Default Color Configuration */

#define LTDC_L1BFCR	(0xA0 + REG_OFS)/* L1 Blend Factors Configuration */

#define LTDC_L1FBBCR	(0xA4 + REG_OFS)/* L1 FrameBuffer Bus Control */

#define LTDC_L1AFBCR	(0xA8 + REG_OFS)/* L1 AuxFB Control */

#define LTDC_L1CFBAR	(0xAC + REG_OFS)/* L1 Color FrameBuffer Address */

#define LTDC_L1CFBLR	(0xB0 + REG_OFS)/* L1 Color FrameBuffer Length */

#define LTDC_L1CFBLNR	(0xB4 + REG_OFS)/* L1 Color FrameBuffer Line Nb */

#define LTDC_L1AFBAR	(0xB8 + REG_OFS)/* L1 AuxFB Address */

#define LTDC_L1AFBLR	(0xBC + REG_OFS)/* L1 AuxFB Length */

#define LTDC_L1AFBLNR	(0xC0 + REG_OFS)/* L1 AuxFB Line Number */

#define LTDC_L1CLUTWR	(0xC4 + REG_OFS)/* L1 CLUT Write */

#define LTDC_L1YS1R	(0xE0 + REG_OFS)/* L1 YCbCr Scale 1 */

#define LTDC_L1YS2R	(0xE4 + REG_OFS)/* L1 YCbCr Scale 2 */



/* Bit definitions */

#define SSCR_VSH	GENMASK(10, 0)	/* Vertical Synchronization Height */
@@ -602,11 +602,11 @@ static void ltdc_plane_atomic_update(struct drm_plane *plane, 
	src_w = state->src_w >> 16;

	src_h = state->src_h >> 16;



	DRM_DEBUG_DRIVER(

		"plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n",

	DRM_DEBUG_DRIVER("plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n",

			 plane->base.id, fb->base.id,

			 src_w, src_h, src_x, src_y,

		state->crtc_w, state->crtc_h, state->crtc_x, state->crtc_y);

			 state->crtc_w, state->crtc_h,

			 state->crtc_x, state->crtc_y);



	bpcr = reg_read(ldev->regs, LTDC_BPCR);

	ahbp = (bpcr & BPCR_AHBP) >> 16;
@@ -645,8 +645,7 @@ static void ltdc_plane_atomic_update(struct drm_plane *plane, 


	/* Specifies the constant alpha value */

	val = CONSTA_MAX;

	reg_update_bits(ldev->regs, LTDC_L1CACR + lofs,

			LXCACR_CONSTA, val);

	reg_update_bits(ldev->regs, LTDC_L1CACR + lofs, LXCACR_CONSTA, val);



	/* Specifies the blending factors */

	val = BF1_PAXCA | BF2_1PAXCA;
@@ -655,8 +654,7 @@ static void ltdc_plane_atomic_update(struct drm_plane *plane, 


	/* Configures the frame buffer line number */

	val = y1 - y0 + 1;

	reg_update_bits(ldev->regs, LTDC_L1CFBLNR + lofs,

			LXCFBLNR_CFBLN, val);

	reg_update_bits(ldev->regs, LTDC_L1CFBLNR + lofs, LXCFBLNR_CFBLN, val);



	/* Sets the FB address */

	paddr = (u32)drm_fb_cma_get_gem_addr(fb, state, 0);