Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 0e1a4200 authored by Shravan Nevatia's avatar Shravan Nevatia
Browse files

ARM: dts: msm: Update cphy_rx_clk_src LOWSVS corner for shima 

- Update the cphy_rx_clk LOWSVS corner values (from 320MHz
to 266.67MHz) in the CSIPHY DT nodes for shima.

- Zero out the rx_clk values in the CSID nodes to ensure
the clk is only set by PHY.

CRs-Fixed: 2792275
Change-Id: Ic39c0123bb04b5b7e449f95823303ca026fa81be
parent 9ea62611

shima-camera.dtsi

+21 −21
Original line number Diff line number Diff line
@@ -40,7 +40,7 @@ 
		src-clock-name = "csi0phytimer_clk_src";

		clock-cntl-level = "lowsvs", "svs";

		clock-rates =

			<320000000 0 300000000 0>,

			<266666667 0 300000000 0>,

			<400000000 0 300000000 0>;

		status = "ok";

	};
@@ -74,7 +74,7 @@ 
		src-clock-name = "csi1phytimer_clk_src";

		clock-cntl-level = "lowsvs", "svs";

		clock-rates =

			<320000000 0 300000000 0>,

			<266666667 0 300000000 0>,

			<400000000 0 300000000 0>;

		status = "ok";

	};
@@ -108,7 +108,7 @@ 
		src-clock-name = "csi2phytimer_clk_src";

		clock-cntl-level = "lowsvs", "svs";

		clock-rates =

			<320000000 0 300000000 0>,

			<266666667 0 300000000 0>,

			<400000000 0 300000000 0>;

		status = "ok";

	};
@@ -142,7 +142,7 @@ 
		src-clock-name = "csi3phytimer_clk_src";

		clock-cntl-level = "lowsvs", "svs";

		clock-rates =

			<320000000 0 300000000 0>,

			<266666667 0 300000000 0>,

			<400000000 0 300000000 0>;

		status = "ok";

	};
@@ -176,7 +176,7 @@ 
		src-clock-name = "csi4phytimer_clk_src";

		clock-cntl-level = "lowsvs", "svs";

		clock-rates =

			<320000000 0 300000000 0>,

			<266666667 0 300000000 0>,

			<400000000 0 300000000 0>;

		status = "ok";

	};
@@ -210,7 +210,7 @@ 
		src-clock-name = "csi5phytimer_clk_src";

		clock-cntl-level = "lowsvs", "svs";

		clock-rates =

			<320000000 0 300000000 0>,

			<266666667 0 300000000 0>,

			<400000000 0 300000000 0>;

		status = "ok";

	};
@@ -707,11 +707,11 @@ 
			<&camcc CAM_CC_IFE_0_AHB_CLK>,

			<&camcc CAM_CC_IFE_0_AXI_CLK>;

		clock-rates =

			<400000000 0 320000000 0 338000000 0 100000000 0 0>,

			<400000000 0 400000000 0 475000000 0 200000000 0 0>,

			<400000000 0 400000000 0 600000000 0 300000000 0 0>,

			<400000000 0 400000000 0 720000000 0 400000000 0 0>,

			<400000000 0 400000000 0 720000000 0 400000000 0 0>;

			<400000000 0 0 0 338000000 0 100000000 0 0>,

			<400000000 0 0 0 475000000 0 200000000 0 0>,

			<400000000 0 0 0 600000000 0 300000000 0 0>,

			<400000000 0 0 0 720000000 0 400000000 0 0>,

			<400000000 0 0 0 720000000 0 400000000 0 0>;

		clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal",

			"turbo";

		src-clock-name = "ife_csid_clk_src";
@@ -794,11 +794,11 @@ 
			<&camcc CAM_CC_IFE_1_AHB_CLK>,

			<&camcc CAM_CC_IFE_1_AXI_CLK>;

		clock-rates =

			<400000000 0 320000000 0 338000000 0 100000000 0 0>,

			<400000000 0 400000000 0 475000000 0 200000000 0 0>,

			<400000000 0 400000000 0 600000000 0 300000000 0 0>,

			<400000000 0 400000000 0 720000000 0 400000000 0 0>,

			<400000000 0 400000000 0 720000000 0 400000000 0 0>;

			<400000000 0 0 0 338000000 0 100000000 0 0>,

			<400000000 0 0 0 475000000 0 200000000 0 0>,

			<400000000 0 0 0 600000000 0 300000000 0 0>,

			<400000000 0 0 0 720000000 0 400000000 0 0>,

			<400000000 0 0 0 720000000 0 400000000 0 0>;

		clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal",

			"turbo";

		src-clock-name = "ife_csid_clk_src";
@@ -881,11 +881,11 @@ 
			<&camcc CAM_CC_IFE_2_AHB_CLK>,

			<&camcc CAM_CC_IFE_2_AXI_CLK>;

		clock-rates =

			<400000000 0 320000000 0 338000000 0 100000000 0 0>,

			<400000000 0 400000000 0 475000000 0 200000000 0 0>,

			<400000000 0 400000000 0 600000000 0 300000000 0 0>,

			<400000000 0 400000000 0 720000000 0 400000000 0 0>,

			<400000000 0 400000000 0 720000000 0 400000000 0 0>;

			<400000000 0 0 0 338000000 0 100000000 0 0>,

			<400000000 0 0 0 475000000 0 200000000 0 0>,

			<400000000 0 0 0 600000000 0 300000000 0 0>,

			<400000000 0 0 0 720000000 0 400000000 0 0>,

			<400000000 0 0 0 720000000 0 400000000 0 0>;

		clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal",

			"turbo";

		src-clock-name = "ife_csid_clk_src";