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Commit 0cf289bd authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Move fence register tracking from i915->mm to ggtt 



As the fence registers only apply to regions inside the GGTT is makes
more sense that we track these as part of the i915_ggtt and not the
general mm. In the next patch, we will then pull the register locking
underneath the i915_ggtt.mutex.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190613073254.24048-1-chris@chris-wilson.co.uk
parent 70972f51

drivers/gpu/drm/i915/gem/i915_gem_mman.c

+2 −2
Original line number Diff line number Diff line
@@ -310,9 +310,9 @@ vm_fault_t i915_gem_fault(struct vm_fault *vmf) 
	/* Mark as being mmapped into userspace for later revocation */

	assert_rpm_wakelock_held(i915);

	if (!i915_vma_set_userfault(vma) && !obj->userfault_count++)

		list_add(&obj->userfault_link, &i915->mm.userfault_list);

		list_add(&obj->userfault_link, &i915->ggtt.userfault_list);

	if (CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND)

		intel_wakeref_auto(&i915->mm.userfault_wakeref,

		intel_wakeref_auto(&i915->ggtt.userfault_wakeref,

				   msecs_to_jiffies_timeout(CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND));

	GEM_BUG_ON(!obj->userfault_count);

drivers/gpu/drm/i915/gem/i915_gem_pm.c

+1 −1
Original line number Diff line number Diff line
@@ -126,7 +126,7 @@ void i915_gem_suspend(struct drm_i915_private *i915) 
{

	GEM_TRACE("\n");



	intel_wakeref_auto(&i915->mm.userfault_wakeref, 0);

	intel_wakeref_auto(&i915->ggtt.userfault_wakeref, 0);

	flush_workqueue(i915->wq);



	mutex_lock(&i915->drm.struct_mutex);

drivers/gpu/drm/i915/gt/intel_reset.c

+3 −3
Original line number Diff line number Diff line
@@ -695,19 +695,19 @@ static void revoke_mmaps(struct drm_i915_private *i915) 
{

	int i;



	for (i = 0; i < i915->num_fence_regs; i++) {

	for (i = 0; i < i915->ggtt.num_fences; i++) {

		struct drm_vma_offset_node *node;

		struct i915_vma *vma;

		u64 vma_offset;



		vma = READ_ONCE(i915->fence_regs[i].vma);

		vma = READ_ONCE(i915->ggtt.fence_regs[i].vma);

		if (!vma)

			continue;



		if (!i915_vma_has_userfault(vma))

			continue;



		GEM_BUG_ON(vma->fence != &i915->fence_regs[i]);

		GEM_BUG_ON(vma->fence != &i915->ggtt.fence_regs[i]);

		node = &vma->obj->base.vma_node;

		vma_offset = vma->ggtt_view.partial.offset << PAGE_SHIFT;

		unmap_mapping_range(i915->drm.anon_inode->i_mapping,

drivers/gpu/drm/i915/gvt/aperture_gm.c

+4 −3
Original line number Diff line number Diff line
@@ -35,6 +35,7 @@ 
 */



#include "i915_drv.h"

#include "i915_gem_fence_reg.h"

#include "gvt.h"



static int alloc_gm(struct intel_vgpu *vgpu, bool high_gm)
@@ -128,7 +129,7 @@ void intel_vgpu_write_fence(struct intel_vgpu *vgpu, 
{

	struct intel_gvt *gvt = vgpu->gvt;

	struct drm_i915_private *dev_priv = gvt->dev_priv;

	struct drm_i915_fence_reg *reg;

	struct i915_fence_reg *reg;

	i915_reg_t fence_reg_lo, fence_reg_hi;



	assert_rpm_wakelock_held(dev_priv);
@@ -163,7 +164,7 @@ static void free_vgpu_fence(struct intel_vgpu *vgpu) 
{

	struct intel_gvt *gvt = vgpu->gvt;

	struct drm_i915_private *dev_priv = gvt->dev_priv;

	struct drm_i915_fence_reg *reg;

	struct i915_fence_reg *reg;

	u32 i;



	if (WARN_ON(!vgpu_fence_sz(vgpu)))
@@ -187,7 +188,7 @@ static int alloc_vgpu_fence(struct intel_vgpu *vgpu) 
{

	struct intel_gvt *gvt = vgpu->gvt;

	struct drm_i915_private *dev_priv = gvt->dev_priv;

	struct drm_i915_fence_reg *reg;

	struct i915_fence_reg *reg;

	int i;



	intel_runtime_pm_get(dev_priv);

drivers/gpu/drm/i915/gvt/gvt.h

+2 −2
Original line number Diff line number Diff line
@@ -87,7 +87,7 @@ struct intel_vgpu_gm { 


/* Fences owned by a vGPU */

struct intel_vgpu_fence {

	struct drm_i915_fence_reg *regs[INTEL_GVT_MAX_NUM_FENCES];

	struct i915_fence_reg *regs[INTEL_GVT_MAX_NUM_FENCES];

	u32 base;

	u32 size;

};
@@ -390,7 +390,7 @@ int intel_gvt_load_firmware(struct intel_gvt *gvt); 
#define gvt_hidden_gmadr_end(gvt) (gvt_hidden_gmadr_base(gvt) \

				   + gvt_hidden_sz(gvt) - 1)



#define gvt_fence_sz(gvt) (gvt->dev_priv->num_fence_regs)

#define gvt_fence_sz(gvt) ((gvt)->dev_priv->ggtt.num_fences)



/* Aperture/GM space definitions for vGPU */

#define vgpu_aperture_offset(vgpu)	((vgpu)->gm.low_gm_node.start)