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Commit 0b9055a1 authored by Moshe Shemesh's avatar Moshe Shemesh Committed by Saeed Mahameed
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net/mlx5: Add core dump register access HW bits



Add Firmware core dump registers and HW definitions.

Signed-off-by: default avatarMoshe Shemesh <moshe@mellanox.com>
Signed-off-by: default avatarEran Ben Elisha <eranbe@mellanox.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@mellanox.com>
parent 6cc070bd
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+1 −0
Original line number Diff line number Diff line
@@ -107,6 +107,7 @@ enum {
	MLX5_REG_FPGA_CAP	 = 0x4022,
	MLX5_REG_FPGA_CTRL	 = 0x4023,
	MLX5_REG_FPGA_ACCESS_REG = 0x4024,
	MLX5_REG_CORE_DUMP	 = 0x402e,
	MLX5_REG_PCAP		 = 0x5001,
	MLX5_REG_PMTU		 = 0x5003,
	MLX5_REG_PTYS		 = 0x5004,
+16 −1
Original line number Diff line number Diff line
@@ -715,7 +715,9 @@ struct mlx5_ifc_qos_cap_bits {
};

struct mlx5_ifc_debug_cap_bits {
	u8         reserved_at_0[0x20];
	u8         core_dump_general[0x1];
	u8         core_dump_qp[0x1];
	u8         reserved_at_2[0x1e];

	u8         reserved_at_20[0x2];
	u8         stall_detect[0x1];
@@ -2531,6 +2533,7 @@ union mlx5_ifc_hca_cap_union_bits {
	struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
	struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
	struct mlx5_ifc_qos_cap_bits qos_cap;
	struct mlx5_ifc_debug_cap_bits debug_cap;
	struct mlx5_ifc_fpga_cap_bits fpga_cap;
	u8         reserved_at_0[0x8000];
};
@@ -8546,6 +8549,18 @@ struct mlx5_ifc_qcam_reg_bits {
	u8         reserved_at_1c0[0x80];
};

struct mlx5_ifc_core_dump_reg_bits {
	u8         reserved_at_0[0x18];
	u8         core_dump_type[0x8];

	u8         reserved_at_20[0x30];
	u8         vhca_id[0x10];

	u8         reserved_at_60[0x8];
	u8         qpn[0x18];
	u8         reserved_at_80[0x180];
};

struct mlx5_ifc_pcap_reg_bits {
	u8         reserved_at_0[0x8];
	u8         local_port[0x8];