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Commit 0b84933d authored by Neil Armstrong's avatar Neil Armstrong
Browse files

drm/meson: fix G12A primary plane disabling 



The G12A Primary plane was disabled by writing in the OSD1 configuration
registers, but this caused the plane blender to stall instead of continuing
to blend only the overlay plane.

Fix this by disabling the OSD1 plane in the blender registers, and also
enabling it back using the same register.

Fixes: 490f50c1 ("drm/meson: Add G12A support for OSD1 Plane")
Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Reviewed-by: default avatarKevin Hilman <khilman@baylibre.com>
[narmstrong: fixed nit in commit log]
Link: https://patchwork.freedesktop.org/patch/msgid/20190605141253.24165-3-narmstrong@baylibre.com
parent c03ea50e

drivers/gpu/drm/meson/meson_crtc.c

+2 −0
Original line number Diff line number Diff line
@@ -252,6 +252,8 @@ static void meson_g12a_crtc_enable_osd1(struct meson_drm *priv) 
	writel_relaxed(priv->viu.osb_blend1_size,

		       priv->io_base +

		       _REG(VIU_OSD_BLEND_BLEND1_SIZE));

	writel_bits_relaxed(3 << 8, 3 << 8,

			    priv->io_base + _REG(OSD1_BLEND_SRC_CTRL));

}



static void meson_crtc_enable_vd1(struct meson_drm *priv)

drivers/gpu/drm/meson/meson_plane.c

+2 −2
Original line number Diff line number Diff line
@@ -318,8 +318,8 @@ static void meson_plane_atomic_disable(struct drm_plane *plane, 


	/* Disable OSD1 */

	if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu"))

		writel_bits_relaxed(BIT(0) | BIT(21), 0,

			priv->io_base + _REG(VIU_OSD1_CTRL_STAT));

		writel_bits_relaxed(3 << 8, 0,

				    priv->io_base + _REG(OSD1_BLEND_SRC_CTRL));

	else

		writel_bits_relaxed(VPP_OSD1_POSTBLEND, 0,

				    priv->io_base + _REG(VPP_MISC));

drivers/gpu/drm/meson/meson_viu.c

+1 −2
Original line number Diff line number Diff line
@@ -405,8 +405,7 @@ void meson_viu_init(struct meson_drm *priv) 
				0 << 16 |

				1,

				priv->io_base + _REG(VIU_OSD_BLEND_CTRL));

		writel_relaxed(3 << 8 |

				1 << 20,

		writel_relaxed(1 << 20,

				priv->io_base + _REG(OSD1_BLEND_SRC_CTRL));

		writel_relaxed(1 << 20,

				priv->io_base + _REG(OSD2_BLEND_SRC_CTRL));