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Commit 0b6d4e66 authored by Tony Truong's avatar Tony Truong
Browse files

ARM: dts: msm: add initial PCIe nodes for lahaina 

Add initial devicetree nodes to support PCIe0 and PCIe1 on
Lahaina.

Change-Id: If0e811a6436ae99018d01a34d131bb06038c80a9
parent 7ff4c2e0

qcom/lahaina-pcie.dtsi

0 → 100644
+296 −0
Original line number Diff line number Diff line 
#include <dt-bindings/clock/qcom,gcc-lahaina.h>



&soc {

	pcie0: qcom,pcie@1c00000 {

		compatible = "qcom,pci-msm";



		reg = <0x01c00000 0x3000>,

			<0x01c06000 0x2000>,

			<0x60000000 0xf1d>,

			<0x60000f20 0xa8>,

			<0x60001000 0x1000>,

			<0x60100000 0x100000>;

		reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";



		cell-index = <0>;

		linux,pci-domain = <0>;



		#address-cells = <3>;

		#size-cells = <2>;

		ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>,

			<0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>;



		interrupt-parent = <&pcie0>;

		interrupts = <0 1 2 3 4>;

		interrupt-names = "int_global_int", "int_a", "int_b", "int_c",

				"int_d";

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 0xffffffff>;



		interrupt-map = <0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH

				0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH

				0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH

				0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH

				0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;



		msi-parent = <&pcie0_msi>;



		perst-gpio = <&tlmm 94 0>;

		wake-gpio = <&tlmm 96 0>;

		pinctrl-names = "default";

		pinctrl-0 = <&pcie0_perst_default

				&pcie0_clkreq_default

				&pcie0_wake_default>;



		gdsc-vdd-supply = <&gcc_pcie_0_gdsc>;

		vreg-1p8-supply = <&pm8350_l6>;

		vreg-0p9-supply = <&pm8350_l5>;

		vreg-cx-supply = <&VDD_CX_LEVEL>;

		qcom,vreg-1p8-voltage-level = <1200000 1200000 25000>;

		qcom,vreg-0p9-voltage-level = <880000 880000 97200>;

		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX

						RPMH_REGULATOR_LEVEL_NOM 0>;

		qcom,bw-scale =

			<RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen1 */

			RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen2 */

			RPMH_REGULATOR_LEVEL_NOM 100000000>; /* Gen3 */



		interconnect-names = "icc_path";

		interconnects = <&aggre2_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;



		clocks = <&clock_gcc GCC_PCIE_0_PIPE_CLK>,

			<&clock_rpmh RPMH_CXO_CLK>,

			<&clock_gcc GCC_PCIE_0_AUX_CLK>,

			<&clock_gcc GCC_PCIE_0_CFG_AHB_CLK>,

			<&clock_gcc GCC_PCIE_0_MSTR_AXI_CLK>,

			<&clock_gcc GCC_PCIE_0_SLV_AXI_CLK>,

			<&clock_gcc GCC_PCIE_0_CLKREF_EN>,

			<&clock_gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,

			<&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,

			<&clock_gcc GCC_PCIE0_PHY_RCHNG_CLK>,

			<&clock_gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;

		clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",

				"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",

				"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",

				"pcie_0_ldo", "pcie_0_slv_q2a_axi_clk",

				"pcie_tbu_clk", "pcie_phy_refgen_clk",

				"pcie_ddrss_sf_tbu_clk";

		max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,

					<0>, <0>, <0>, <0>, <100000000>, <0>;



		resets = <&clock_gcc GCC_PCIE_0_BCR>,

			<&clock_gcc GCC_PCIE_0_PHY_BCR>;

		reset-names = "pcie_0_core_reset",

				"pcie_0_phy_reset";



		dma-coherent;

		qcom,smmu-sid-base = <0x1c00>;

		iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,

			<0x100 &apps_smmu 0x1c01 0x1>;



		qcom,boot-option = <0x1>;

		qcom,drv-supported;

		qcom,drv-l1ss-timeout-us = <10000>;

		qcom,use-19p2mhz-aux-clk;

		qcom,no-l0s-supported;

		qcom,l1-2-th-scale = <2>;

		qcom,l1-2-th-value = <70>;

		qcom,slv-addr-space-size = <0x4000000>;

		qcom,ep-latency = <10>;



		qcom,pcie-phy-ver = <0>;

		qcom,phy-status-offset = <0x214>;

		qcom,phy-status-bit = <6>;

		qcom,phy-power-down-offset = <0x240>;

		qcom,phy-sequence = <0 0 0>;



		status = "disabled";



		pcie0_rp: pcie0_rp {

			reg = <0 0 0 0 0>;

		};

	};



	pcie0_msi: qcom,pcie0_msi@17a10040 {

		compatible = "qcom,pci-msi";

		msi-controller;

		reg = <0x17a10040 0x0>;

		interrupt-parent = <&intc>;

		interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;

	};



	pcie1: qcom,pcie@1c08000 {

		compatible = "qcom,pci-msm";



		reg = <0x01c08000 0x3000>,

			<0x01c0e000 0x2000>,

			<0x40000000 0xf1d>,

			<0x40000f20 0xa8>,

			<0x40001000 0x1000>,

			<0x40100000 0x100000>;

		reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";



		cell-index = <1>;

		linux,pci-domain = <1>;



		#address-cells = <3>;

		#size-cells = <2>;

		ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,

			<0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>;



		interrupt-parent = <&pcie1>;

		interrupts = <0 1 2 3 4>;

		interrupt-names = "int_global_int", "int_a", "int_b", "int_c",

				"int_d";

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 0xffffffff>;

		interrupt-map = <0 0 0 0 &intc GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH

				0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH

				0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH

				0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH

				0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;

		msi-parent = <&pcie1_msi>;



		perst-gpio = <&tlmm 97 0>;

		wake-gpio = <&tlmm 99 0>;

		pinctrl-names = "default";

		pinctrl-0 = <&pcie1_perst_default

				&pcie1_clkreq_default

				&pcie1_wake_default>;



		gdsc-vdd-supply = <&gcc_pcie_1_gdsc>;

		vreg-1p8-supply = <&pm8350_l6>;

		vreg-0p9-supply = <&pm8350_l5>;

		vreg-cx-supply = <&VDD_CX_LEVEL>;

		qcom,vreg-1p8-voltage-level = <1200000 1200000 25000>;

		qcom,vreg-0p9-voltage-level = <880000 880000 97200>;

		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX

						RPMH_REGULATOR_LEVEL_NOM 0>;

		qcom,bw-scale =

			<RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen1 */

			RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen2 */

			RPMH_REGULATOR_LEVEL_NOM 100000000>; /* Gen3 */



		interconnect-names = "icc_path";

		interconnects = <&aggre2_noc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>;



		clocks = <&clock_gcc GCC_PCIE_1_PIPE_CLK>,

			<&clock_rpmh RPMH_CXO_CLK>,

			<&clock_gcc GCC_PCIE_1_AUX_CLK>,

			<&clock_gcc GCC_PCIE_1_CFG_AHB_CLK>,

			<&clock_gcc GCC_PCIE_1_MSTR_AXI_CLK>,

			<&clock_gcc GCC_PCIE_1_SLV_AXI_CLK>,

			<&clock_gcc GCC_PCIE_1_CLKREF_EN>,

			<&clock_gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,

			<&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,

			<&clock_gcc GCC_PCIE1_PHY_RCHNG_CLK>,

			<&clock_gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;

		clock-names = "pcie_1_pipe_clk", "pcie_1_ref_clk_src",

				"pcie_1_aux_clk", "pcie_1_cfg_ahb_clk",

				"pcie_1_mstr_axi_clk", "pcie_1_slv_axi_clk",

				"pcie_1_ldo", "pcie_1_slv_q2a_axi_clk",

				"pcie_tbu_clk", "pcie_phy_refgen_clk",

				"pcie_ddrss_sf_tbu_clk";

		max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,

					<0>, <0>, <0>, <0>, <100000000>, <0>;



		resets = <&clock_gcc GCC_PCIE_1_BCR>,

			<&clock_gcc GCC_PCIE_1_PHY_BCR>;

		reset-names = "pcie_1_core_reset",

				"pcie_1_phy_reset";



		dma-coherent;

		qcom,smmu-sid-base = <0x1c80>;

		iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,

			<0x100 &apps_smmu 0x1c81 0x1>;



		qcom,boot-option = <0x1>;

		qcom,drv-supported;

		qcom,use-19p2mhz-aux-clk;

		qcom,no-l0s-supported;

		qcom,slv-addr-space-size = <0x20000000>;

		qcom,ep-latency = <10>;



		qcom,pcie-phy-ver = <0>;

		qcom,phy-status-offset = <0x214>;

		qcom,phy-status-bit = <6>;

		qcom,phy-power-down-offset = <0x240>;

		qcom,phy-sequence = <0 0 0>;



		status = "disabled";



		pcie1_rp: pcie1_rp {

			reg = <0 0 0 0 0>;

		};

	};



	pcie1_msi: qcom,pcie1_msi@17a10040 {

		compatible = "qcom,pci-msi";

		msi-controller;

		reg = <0x17a10040 0x0>;

		interrupt-parent = <&intc>;

		interrupts = <GIC_SPI 800 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 801 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 802 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 803 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 804 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 805 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 806 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 807 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 808 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 809 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 810 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 811 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 812 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 813 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 814 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 815 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 816 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 817 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 818 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 819 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 820 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 821 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 822 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 823 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 824 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 825 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 826 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 827 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 828 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 829 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 830 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 831 IRQ_TYPE_EDGE_RISING>;

	};

};

qcom/lahaina-pinctrl.dtsi

+82 −0
Original line number Diff line number Diff line
@@ -1342,6 +1342,88 @@ 
				};

			};

		};



		pcie0 {

			pcie0_perst_default: pcie0_perst_default {

				mux {

					pins = "gpio94";

					function = "gpio";

				};



				config {

					pins = "gpio94";

					drive-strength = <2>;

					bias-pull-down;

				};

			};



			pcie0_clkreq_default: pcie0_clkreq_default {

				mux {

					pins = "gpio95";

					function = "pci_e0";

				};



				config {

					pins = "gpio95";

					drive-strength = <2>;

					bias-pull-up;

				};

			};



			pcie0_wake_default: pcie0_wake_default {

				mux {

					pins = "gpio96";

					function = "gpio";

				};



				config {

					pins = "gpio96";

					drive-strength = <2>;

					bias-pull-up;

				};

			};

		};



		pcie1 {

			pcie1_perst_default: pcie1_perst_default {

				mux {

					pins = "gpio97";

					function = "gpio";

				};



				config {

					pins = "gpio97";

					drive-strength = <2>;

					bias-pull-down;

				};

			};



			pcie1_clkreq_default: pcie1_clkreq_default {

				mux {

					pins = "gpio98";

					function = "pci_e1";

				};



				config {

					pins = "gpio98";

					drive-strength = <2>;

					bias-pull-up;

				};

			};



			pcie1_wake_default: pcie1_wake_default {

				mux {

					pins = "gpio99";

					function = "gpio";

				};



				config {

					pins = "gpio99";

					drive-strength = <2>;

					bias-pull-up;

				};

			};

		};

	};



	cam_sensor_mclk0_active: cam_sensor_mclk0_active {

qcom/lahaina.dtsi

+3 −0
Original line number Diff line number Diff line
@@ -34,6 +34,8 @@ 
	aliases {

		ufshc1 = &ufshc_mem; /* Embedded UFS Slot */

		serial0 = &qupv3_se3_2uart;

		pci-domain0 = &pcie0; /* PCIe0 domain */

		pci-domain1 = &pcie1; /* PCIe1 domain */

	};



	cpus {
@@ -2210,3 +2212,4 @@ 
#include "lahaina-qupv3.dtsi"

#include "lahaina-vidc.dtsi"

#include "lahaina-cvp.dtsi"

#include "lahaina-pcie.dtsi"