Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 0b066d63 authored by Vivek Aknurwar's avatar Vivek Aknurwar
Browse files

clk: qcom: clk-rcg2: Add support to print rcg's CMD_DFSR register 



Add support to print rcg's CMD_DFSR register. DFS_EN bit 0 of CMD_DFSR
register indicates clk DFS mode.

Change-Id: I5d98550f89bdd14496f94edc455d67f61a1566a4
Signed-off-by: default avatarVivek Aknurwar <viveka@codeaurora.org>
parent da558fde

drivers/clk/qcom/clk-rcg.h

+2 −1
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/* Copyright (c) 2013, 2016-2019, The Linux Foundation. All rights reserved. */

/* Copyright (c) 2013, 2016-2020, The Linux Foundation. All rights reserved. */



#ifndef __QCOM_CLK_RCG_H__

#define __QCOM_CLK_RCG_H__
@@ -159,6 +159,7 @@ struct clk_rcg2 { 
	u8			flags;

#define FORCE_ENABLE_RCG	BIT(0)

#define HW_CLK_CTRL_MODE	BIT(1)

#define DFS_SUPPORT		BIT(2)

};



#define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr)

drivers/clk/qcom/clk-rcg2.c

+30 −17
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2013, 2016-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2013, 2016-2020, The Linux Foundation. All rights reserved.

 */



#include <linux/kernel.h>
@@ -451,36 +451,47 @@ static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) 
static void clk_rcg2_list_registers(struct seq_file *f, struct clk_hw *hw)

{

	struct clk_rcg2 *rcg = to_clk_rcg2(hw);

	int i = 0, size = 0, val;

	static struct clk_register_data *data;

	int i, val;



	static struct clk_register_data data[] = {

	static struct clk_register_data data1[] = {

		{"CMD_RCGR", 0x0},

		{"CFG_RCGR", 0x4},

		{ },

	};



	static struct clk_register_data data1[] = {

	static struct clk_register_data data2[] = {

		{"CMD_RCGR", 0x0},

		{"CFG_RCGR", 0x4},

		{"M_VAL", 0x8},

		{"N_VAL", 0xC},

		{"D_VAL", 0x10},

		{ },

	};



	if (rcg->mnd_width) {

		size = ARRAY_SIZE(data1);

		for (i = 0; i < size; i++) {

			regmap_read(rcg->clkr.regmap, (rcg->cmd_rcgr +

					data1[i].offset), &val);

			seq_printf(f, "%20s: 0x%.8x\n",	data1[i].name, val);

		}

	} else {

		size = ARRAY_SIZE(data);

		for (i = 0; i < size; i++) {

	static struct clk_register_data data3[] = {

		{"CMD_RCGR", 0x0},

		{"CFG_RCGR", 0x4},

		{"M_VAL", 0x8},

		{"N_VAL", 0xC},

		{"D_VAL", 0x10},

		{"CMD_DFSR", 0x14},

		{ },

	};



	if (rcg->flags & DFS_SUPPORT)

		data = data3;

	else if (rcg->mnd_width)

		data = data2;

	else

		data = data1;



	for (i = 0; data[i].name != NULL; i++) {

		regmap_read(rcg->clkr.regmap, (rcg->cmd_rcgr +

				data[i].offset), &val);

		seq_printf(f, "%20s: 0x%.8x\n", data[i].name, val);

	}

	}



}



/* Return the nth supported frequency for a given clock. */
@@ -1590,6 +1601,8 @@ static int clk_rcg2_enable_dfs(const struct clk_rcg_dfs_data *data, 
	u32 val;

	int ret;



	rcg->flags |= DFS_SUPPORT;



	ret = regmap_read(regmap, rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, &val);

	if (ret)

		return -EINVAL;