Loading qcom/lahaina.dtsi +0 −3 Original line number Diff line number Diff line Loading @@ -1498,7 +1498,6 @@ lanes-per-direction = <2>; limit-rate = <1>; /* HS Rate-A */ dev-ref-clk-freq = <0>; /* 19.2 MHz */ qcom,disable-lpm; clock-names = "core_clk", "bus_aggr_clk", Loading Loading @@ -1594,8 +1593,6 @@ resets = <&clock_gcc GCC_UFS_PHY_BCR>; reset-names = "rst"; dma-coherent; limit-tx-hs-gear = <3>; limit-rx-hs-gear = <3>; status = "disabled"; }; Loading Loading
qcom/lahaina.dtsi +0 −3 Original line number Diff line number Diff line Loading @@ -1498,7 +1498,6 @@ lanes-per-direction = <2>; limit-rate = <1>; /* HS Rate-A */ dev-ref-clk-freq = <0>; /* 19.2 MHz */ qcom,disable-lpm; clock-names = "core_clk", "bus_aggr_clk", Loading Loading @@ -1594,8 +1593,6 @@ resets = <&clock_gcc GCC_UFS_PHY_BCR>; reset-names = "rst"; dma-coherent; limit-tx-hs-gear = <3>; limit-rx-hs-gear = <3>; status = "disabled"; }; Loading