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Commit 0acb69e7 authored by Lubomir Rintel's avatar Lubomir Rintel Committed by Stephen Boyd
Browse files

Revert "clk: mmp2: add SP clock" 

It seems that the kernel has no business managing this clock: once the SP
clock is disabled, it's not sufficient to just enable in order to bring the
SP core back up. Just let the firmware keep it enabled and don't expose it
to drivers.

This reverts commit fc27c239.

Link: https://lore.kernel.org/lkml/154783267051.169631.3197836544646625747@swboyd.mtv.corp.google.com/


Signed-off-by: default avatarLubomir Rintel <lkundrak@v3.sk>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 0113613f

drivers/clk/mmp/clk-of-mmp2.c

+0 −4
Original line number Diff line number Diff line
@@ -53,7 +53,6 @@ 
#define APMU_DISP1	0x110

#define APMU_CCIC0	0x50

#define APMU_CCIC1	0xf4

#define APMU_SP		0x68

#define MPMU_UART_PLL	0x14



struct mmp2_clk_unit {
@@ -210,8 +209,6 @@ static struct mmp_clk_mix_config ccic1_mix_config = { 
	.reg_info = DEFINE_MIX_REG_INFO(4, 16, 2, 6, 32),

};



static DEFINE_SPINLOCK(sp_lock);



static struct mmp_param_mux_clk apmu_mux_clks[] = {

	{MMP2_CLK_DISP0_MUX, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0, 6, 2, 0, &disp0_lock},

	{MMP2_CLK_DISP1_MUX, "disp1_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP1, 6, 2, 0, &disp1_lock},
@@ -242,7 +239,6 @@ static struct mmp_param_gate_clk apmu_gate_clks[] = { 
	{MMP2_CLK_CCIC1, "ccic1_clk", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x1b, 0x1b, 0x0, 0, &ccic1_lock},

	{MMP2_CLK_CCIC1_PHY, "ccic1_phy_clk", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x24, 0x24, 0x0, 0, &ccic1_lock},

	{MMP2_CLK_CCIC1_SPHY, "ccic1_sphy_clk", "ccic1_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x300, 0x300, 0x0, 0, &ccic1_lock},

	{MMP2_CLK_SP, "sp_clk", NULL, CLK_SET_RATE_PARENT, APMU_SP, 0x1b, 0x1b, 0x0, 0, &sp_lock},

};



static void mmp2_axi_periph_clk_init(struct mmp2_clk_unit *pxa_unit)