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Commit 0a6abefe authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amd/powerplay: fix typo error when set clock gate state. 



Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: default avatarChristian <König&lt;christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b7e2e9f7

drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c

+1 −1
Original line number Diff line number Diff line
@@ -56,7 +56,7 @@ int fiji_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) 
		fiji_update_uvd_dpm(hwmgr, false);

		cgs_set_clockgating_state(hwmgr->device,

					  AMD_IP_BLOCK_TYPE_UVD,

					  AMD_PG_STATE_UNGATE);

					  AMD_CG_STATE_UNGATE);

	}



	return 0;

drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c

+1 −1
Original line number Diff line number Diff line
@@ -116,7 +116,7 @@ int polaris10_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) 
		polaris10_update_uvd_dpm(hwmgr, false);

		cgs_set_clockgating_state(hwmgr->device,

				AMD_IP_BLOCK_TYPE_UVD,

				AMD_PG_STATE_UNGATE);

				AMD_CG_STATE_UNGATE);

	}



	return 0;