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Commit 0a59952b authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Configure SKL+ scaler initial phase correctly 



Set up the SKL+ scaler initial phase registers correctly. Otherwise
we start fetching the data from the center of the first pixel instead
of the top-left corner, which obviously then leads to right/bottom edges
replicating data excessively as the data runs out half a pixel too soon.

Cc: Vidya Srinivas <vidya.srinivas@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180521185613.5097-2-ville.syrjala@linux.intel.com


Reviewed-By: default avatarVidya Srinivas <vidya.srinivas@intel.com>
parent 012d79e6

drivers/gpu/drm/i915/i915_reg.h

+4 −0
Original line number Diff line number Diff line
@@ -6789,6 +6789,10 @@ enum { 
#define _PS_VPHASE_1B       0x68988

#define _PS_VPHASE_2B       0x68A88

#define _PS_VPHASE_1C       0x69188

#define  PS_Y_PHASE(x)		((x) << 16)

#define  PS_UV_RGB_PHASE(x)	((x) << 0)

#define   PS_PHASE_MASK	(0x7fff << 1) /* u2.13 */

#define   PS_PHASE_TRIP	(1 << 0)



#define _PS_HPHASE_1A       0x68194

#define _PS_HPHASE_2A       0x68294

drivers/gpu/drm/i915/intel_display.c

+41 −0
Original line number Diff line number Diff line
@@ -4752,6 +4752,39 @@ static void cpt_verify_modeset(struct drm_device *dev, int pipe) 
	}

}



/*

 * The hardware phase 0.0 refers to the center of the pixel.

 * We want to start from the top/left edge which is phase

 * -0.5. That matches how the hardware calculates the scaling

 * factors (from top-left of the first pixel to bottom-right

 * of the last pixel, as opposed to the pixel centers).

 *

 * For 4:2:0 subsampled chroma planes we obviously have to

 * adjust that so that the chroma sample position lands in

 * the right spot.

 *

 * Note that for packed YCbCr 4:2:2 formats there is no way to

 * control chroma siting. The hardware simply replicates the

 * chroma samples for both of the luma samples, and thus we don't

 * actually get the expected MPEG2 chroma siting convention :(

 * The same behaviour is observed on pre-SKL platforms as well.

 */

u16 skl_scaler_calc_phase(int sub, bool chroma_cosited)

{

	int phase = -0x8000;

	u16 trip = 0;



	if (chroma_cosited)

		phase += (sub - 1) * 0x8000 / sub;



	if (phase < 0)

		phase = 0x10000 + phase;

	else

		trip = PS_PHASE_TRIP;



	return ((phase >> 2) & PS_PHASE_MASK) | trip;

}



static int

skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,

		  unsigned int scaler_user, int *scaler_id,
@@ -4951,14 +4984,22 @@ static void skylake_pfit_enable(struct intel_crtc *crtc) 
		&crtc->config->scaler_state;



	if (crtc->config->pch_pfit.enabled) {

		u16 uv_rgb_hphase, uv_rgb_vphase;

		int id;



		if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))

			return;



		uv_rgb_hphase = skl_scaler_calc_phase(1, false);

		uv_rgb_vphase = skl_scaler_calc_phase(1, false);



		id = scaler_state->scaler_id;

		I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |

			PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);

		I915_WRITE_FW(SKL_PS_VPHASE(pipe, id),

			      PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));

		I915_WRITE_FW(SKL_PS_HPHASE(pipe, id),

			      PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));

		I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);

		I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);

	}

drivers/gpu/drm/i915/intel_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -1616,6 +1616,7 @@ void intel_mode_from_pipe_config(struct drm_display_mode *mode, 
void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,

				  struct intel_crtc_state *crtc_state);



u16 skl_scaler_calc_phase(int sub, bool chroma_center);

int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);

int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,

		  uint32_t pixel_format);

drivers/gpu/drm/i915/intel_sprite.c

+24 −2
Original line number Diff line number Diff line
@@ -284,13 +284,35 @@ skl_update_plane(struct intel_plane *plane, 
	/* program plane scaler */

	if (plane_state->scaler_id >= 0) {

		int scaler_id = plane_state->scaler_id;

		const struct intel_scaler *scaler;

		const struct intel_scaler *scaler =

			&crtc_state->scaler_state.scalers[scaler_id];

		u16 y_hphase, uv_rgb_hphase;

		u16 y_vphase, uv_rgb_vphase;



		/* TODO: handle sub-pixel coordinates */

		if (fb->format->format == DRM_FORMAT_NV12) {

			y_hphase = skl_scaler_calc_phase(1, false);

			y_vphase = skl_scaler_calc_phase(1, false);



			/* MPEG2 chroma siting convention */

			uv_rgb_hphase = skl_scaler_calc_phase(2, true);

			uv_rgb_vphase = skl_scaler_calc_phase(2, false);

		} else {

			/* not used */

			y_hphase = 0;

			y_vphase = 0;



		scaler = &crtc_state->scaler_state.scalers[scaler_id];

			uv_rgb_hphase = skl_scaler_calc_phase(1, false);

			uv_rgb_vphase = skl_scaler_calc_phase(1, false);

		}



		I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id),

			      PS_SCALER_EN | PS_PLANE_SEL(plane_id) | scaler->mode);

		I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);

		I915_WRITE_FW(SKL_PS_VPHASE(pipe, scaler_id),

			      PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase));

		I915_WRITE_FW(SKL_PS_HPHASE(pipe, scaler_id),

			      PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase));

		I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);

		I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id),

			      ((crtc_w + 1) << 16)|(crtc_h + 1));