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Commit 0980a60f authored by Chris Wilson's avatar Chris Wilson Committed by Daniel Vetter
Browse files

drm/i915: Acquire dpio_lock for VLV sideband programming in DP/HDMI 



Otherwise we get flooded by the kernel warning us that we are doing
long sequences of IO without serialisation. For example,

 WARNING: CPU: 0 PID: 11136 at drivers/gpu/drm/i915/intel_sideband.c:40 vlv_sideband_rw+0x48/0x1ef()
 Modules linked in:
 CPU: 0 PID: 11136 Comm: kworker/u2:0 Tainted: G        W    3.11.0-rc2+ #4
 Call Trace:
  [<c2028564>] ?  warn_slowpath_common+0x63/0x78
  [<c227ad43>] ?  vlv_sideband_rw+0x48/0x1ef
  [<c20285dd>] ?  warn_slowpath_null+0xf/0x13
  [<c227ad43>] ?  vlv_sideband_rw+0x48/0x1ef
  [<c227b060>] ?  vlv_dpio_write+0x1c/0x21
  [<c2262b3b>] ?  intel_dp_set_signal_levels+0x24a/0x385
  [<c2264909>] ?  intel_dp_complete_link_train+0x25/0x1d1
  [<c2264c55>] ?  intel_dp_check_link_status+0xf7/0x106
  [<c2238ced>] ?  i915_hotplug_work_func+0x17b/0x221
  [<c203a204>] ?  process_one_work+0x12e/0x210
  [<c203a5e4>] ?  worker_thread+0x116/0x1ad
  [<c203a4ce>] ?  rescuer_thread+0x1cb/0x1cb
  [<c203d8f5>] ?  kthread+0x67/0x6c
  [<c2457ebb>] ?  ret_from_kernel_thread+0x1b/0x30
  [<c203d88e>] ?  init_completion+0x18/0x18

v2: Retire the locking in vlv_crtc_enable() and do it close to the meat.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
[danvet: Squash in a s/mutex_lock/mutex_unlock/ fixup spotted by the 0
day kernel build/coccinelle and reported by Dan Carpenter.]
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent b6dfdc9b

drivers/gpu/drm/i915/intel_display.c

+0 −4
Original line number Diff line number Diff line
@@ -3652,8 +3652,6 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc) 
	intel_crtc->active = true;

	intel_update_watermarks(dev);



	mutex_lock(&dev_priv->dpio_lock);



	for_each_encoder_on_crtc(dev, crtc, encoder)

		if (encoder->pre_pll_enable)

			encoder->pre_pll_enable(encoder);
@@ -3678,8 +3676,6 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc) 
	intel_crtc_update_cursor(crtc, true);



	intel_update_fbc(dev);



	mutex_unlock(&dev_priv->dpio_lock);

}



static void i9xx_crtc_enable(struct drm_crtc *crtc)

drivers/gpu/drm/i915/intel_dp.c

+6 −0
Original line number Diff line number Diff line
@@ -1727,6 +1727,7 @@ static void intel_pre_enable_dp(struct intel_encoder *encoder) 
		int pipe = intel_crtc->pipe;

		u32 val;



		mutex_lock(&dev_priv->dpio_lock);

		val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));

		val = 0;

		if (pipe)
@@ -1740,6 +1741,7 @@ static void intel_pre_enable_dp(struct intel_encoder *encoder) 
				 0x00760018);

		vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),

				 0x00400888);

		mutex_unlock(&dev_priv->dpio_lock);

	}

}
@@ -1754,6 +1756,7 @@ static void intel_dp_pre_pll_enable(struct intel_encoder *encoder) 
		return;



	/* Program Tx lane resets to default */

	mutex_lock(&dev_priv->dpio_lock);

	vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),

			 DPIO_PCS_TX_LANE2_RESET |

			 DPIO_PCS_TX_LANE1_RESET);
@@ -1767,6 +1770,7 @@ static void intel_dp_pre_pll_enable(struct intel_encoder *encoder) 
	vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);

	vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);

	vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);

	mutex_unlock(&dev_priv->dpio_lock);

}



/*
@@ -1978,6 +1982,7 @@ static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp) 
		return 0;

	}



	mutex_lock(&dev_priv->dpio_lock);

	vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);

	vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);

	vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
@@ -1986,6 +1991,7 @@ static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp) 
	vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);

	vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);

	vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);

	mutex_unlock(&dev_priv->dpio_lock);



	return 0;

}

drivers/gpu/drm/i915/intel_hdmi.c

+4 −0
Original line number Diff line number Diff line
@@ -1019,6 +1019,7 @@ static void intel_hdmi_pre_enable(struct intel_encoder *encoder) 
		return;



	/* Enable clock channels for this port */

	mutex_lock(&dev_priv->dpio_lock);

	val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));

	val = 0;

	if (pipe)
@@ -1049,6 +1050,7 @@ static void intel_hdmi_pre_enable(struct intel_encoder *encoder) 
			 0x00760018);

	vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),

			 0x00400888);

	mutex_unlock(&dev_priv->dpio_lock);

}



static void intel_hdmi_pre_pll_enable(struct intel_encoder *encoder)
@@ -1062,6 +1064,7 @@ static void intel_hdmi_pre_pll_enable(struct intel_encoder *encoder) 
		return;



	/* Program Tx lane resets to default */

	mutex_lock(&dev_priv->dpio_lock);

	vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),

			 DPIO_PCS_TX_LANE2_RESET |

			 DPIO_PCS_TX_LANE1_RESET);
@@ -1080,6 +1083,7 @@ static void intel_hdmi_pre_pll_enable(struct intel_encoder *encoder) 
			 0x00002000);

	vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port),

			 DPIO_TX_OCALINIT_EN);

	mutex_unlock(&dev_priv->dpio_lock);

}



static void intel_hdmi_post_disable(struct intel_encoder *encoder)