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Commit 092a95d4 authored by Andi Kleen's avatar Andi Kleen
Browse files

perf vendor events intel: Add uncore events for Broadwell client 

Add V18 of Broadwell uncore events

Cc: jolsa@kernel.org
Link: http://lkml.kernel.org/n/tip-xlbguqdzho7l3qn7di40a7av@git.kernel.org


Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
parent 0585c626

tools/perf/pmu-events/arch/x86/broadwell/uncore.json

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+278 −0
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[

  {

    "Unit": "CBO",

    "EventCode": "0x22",

    "UMask": "0x41",

    "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE",

    "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",

    "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x22",

    "UMask": "0x81",

    "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION",

    "BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",

    "PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x22",

    "UMask": "0x44",

    "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE",

    "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",

    "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x22",

    "UMask": "0x48",

    "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE",

    "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",

    "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x34",

    "UMask": "0x11",

    "EventName": "UNC_CBO_CACHE_LOOKUP.READ_M",

    "BriefDescription": "L3 Lookup read request that access cache and found line in M-state",

    "PublicDescription": "L3 Lookup read request that access cache and found line in M-state.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x34",

    "UMask": "0x21",

    "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M",

    "BriefDescription": "L3 Lookup write request that access cache and found line in M-state",

    "PublicDescription": "L3 Lookup write request that access cache and found line in M-state.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x34",

    "UMask": "0x81",

    "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M",

    "BriefDescription": "L3 Lookup any request that access cache and found line in M-state",

    "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x34",

    "UMask": "0x18",

    "EventName": "UNC_CBO_CACHE_LOOKUP.READ_I",

    "BriefDescription": "L3 Lookup read request that access cache and found line in I-state",

    "PublicDescription": "L3 Lookup read request that access cache and found line in I-state.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x34",

    "UMask": "0x88",

    "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I",

    "BriefDescription": "L3 Lookup any request that access cache and found line in I-state",

    "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x34",

    "UMask": "0x1f",

    "EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI",

    "BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state",

    "PublicDescription": "L3 Lookup read request that access cache and found line in any MESI-state.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x34",

    "UMask": "0x2f",

    "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI",

    "BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state",

    "PublicDescription": "L3 Lookup write request that access cache and found line in MESI-state.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x34",

    "UMask": "0x8f",

    "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI",

    "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state",

    "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x34",

    "UMask": "0x86",

    "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES",

    "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state",

    "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x34",

    "UMask": "0x16",

    "EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES",

    "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state",

    "PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x34",

    "UMask": "0x26",

    "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES",

    "BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state",

    "PublicDescription": "L3 Lookup write request that access cache and found line in E or S-state.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "iMPH-U",

    "EventCode": "0x80",

    "UMask": "0x01",

    "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",

    "BriefDescription": "Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",

    "PublicDescription": "Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",

    "Counter": "0,",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "iMPH-U",

    "EventCode": "0x80",

    "UMask": "0x02",

    "EventName": "UNC_ARB_TRK_OCCUPANCY.DRD_DIRECT",

    "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case.",

    "PublicDescription": "Each cycle count number of 'valid' coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case.",

    "Counter": "0,",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "iMPH-U",

    "EventCode": "0x81",

    "UMask": "0x01",

    "EventName": "UNC_ARB_TRK_REQUESTS.ALL",

    "BriefDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",

    "PublicDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "iMPH-U",

    "EventCode": "0x81",

    "UMask": "0x02",

    "EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT",

    "BriefDescription": "Number of Core coherent Data Read entries allocated in DirectData mode",

    "PublicDescription": "Number of Core coherent Data Read entries allocated in DirectData mode.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "iMPH-U",

    "EventCode": "0x81",

    "UMask": "0x20",

    "EventName": "UNC_ARB_TRK_REQUESTS.WRITES",

    "BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",

    "PublicDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "iMPH-U",

    "EventCode": "0x84",

    "UMask": "0x01",

    "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",

    "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",

    "PublicDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "iMPH-U",

    "EventCode": "0x80",

    "UMask": "0x01",

    "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",

    "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.;",

    "PublicDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",

    "Counter": "0,",

    "CounterMask": "1",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "NCU",

    "EventCode": "0x0",

    "UMask": "0x01",

    "EventName": "UNC_CLOCK.SOCKET",

    "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles",

    "PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.",

    "Counter": "FIXED",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  }

]
 
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