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Commit 09209662 authored by Dhinakaran Pandiyan's avatar Dhinakaran Pandiyan
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drm/i915: Fix VIDEO_DIP_CTL bit shifts 



The shifts for VSC_SELECT bits are wrong, fix it. Good thing is the
definitions are unused.

v2: Moves definitions in another patch (Manasi)
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Fixes: 7af2be6d ("drm/i915/icl: Add VIDEO_DIP registers")
Signed-off-by: default avatarDhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: default avatarManasi Navare <manasi.d.navare@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181005185643.31660-1-dhinakaran.pandiyan@intel.com
parent 1ca2b067

drivers/gpu/drm/i915/i915_reg.h

+6 −6
Original line number Diff line number Diff line
@@ -4573,12 +4573,12 @@ enum { 


#define  DRM_DIP_ENABLE			(1 << 28)

#define  PSR_VSC_BIT_7_SET		(1 << 27)

#define  VSC_SELECT_MASK		(0x3 << 26)

#define  VSC_SELECT_SHIFT		26

#define  VSC_DIP_HW_HEA_DATA		(0 << 26)

#define  VSC_DIP_HW_HEA_SW_DATA		(1 << 26)

#define  VSC_DIP_HW_DATA_SW_HEA		(2 << 26)

#define  VSC_DIP_SW_HEA_DATA		(3 << 26)

#define  VSC_SELECT_MASK		(0x3 << 25)

#define  VSC_SELECT_SHIFT		25

#define  VSC_DIP_HW_HEA_DATA		(0 << 25)

#define  VSC_DIP_HW_HEA_SW_DATA		(1 << 25)

#define  VSC_DIP_HW_DATA_SW_HEA		(2 << 25)

#define  VSC_DIP_SW_HEA_DATA		(3 << 25)

#define  VDIP_ENABLE_PPS		(1 << 24)



/* Panel power sequencing */