omapdss: HDMI: move common functions to a separate file (08d83e4e) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/video/omap2/dss/Makefile

+2 −2

Original line number	Original line	Diff line number	Diff line
	@@ -10,6 +10,6 @@ omapdss-$(CONFIG_OMAP2_DSS_RFBI) += rfbi.o
	omapdss-$(CONFIG_OMAP2_DSS_VENC) += venc.o		omapdss-$(CONFIG_OMAP2_DSS_VENC) += venc.o
	omapdss-$(CONFIG_OMAP2_DSS_SDI) += sdi.o		omapdss-$(CONFIG_OMAP2_DSS_SDI) += sdi.o
	omapdss-$(CONFIG_OMAP2_DSS_DSI) += dsi.o		omapdss-$(CONFIG_OMAP2_DSS_DSI) += dsi.o
	omapdss-$(CONFIG_OMAP4_DSS_HDMI) += hdmi4.o hdmi_wp.o hdmi_pll.o hdmi_phy.o \		omapdss-$(CONFIG_OMAP4_DSS_HDMI) += hdmi4.o hdmi_common.o hdmi_wp.o hdmi_pll.o \
	hdmi4_core.o		hdmi_phy.o hdmi4_core.o
	ccflags-$(CONFIG_OMAP2_DSS_DEBUG) += -DDEBUG		ccflags-$(CONFIG_OMAP2_DSS_DEBUG) += -DDEBUG

drivers/video/omap2/dss/hdmi.h

+10 −1

Original line number	Original line	Diff line number	Diff line
	@@ -423,13 +423,22 @@ void hdmi_phy_disable(struct hdmi_phy_data phy, struct hdmi_wp_data wp);
	void hdmi_phy_dump(struct hdmi_phy_data phy, struct seq_file s);		void hdmi_phy_dump(struct hdmi_phy_data phy, struct seq_file s);
	int hdmi_phy_init(struct platform_device pdev, struct hdmi_phy_data phy);		int hdmi_phy_init(struct platform_device pdev, struct hdmi_phy_data phy);

			/* HDMI common funcs */
			const struct hdmi_config *hdmi_default_timing(void);
			const struct hdmi_config *hdmi_get_timings(int mode, int code);
			struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing);

	#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)		#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
	int hdmi_compute_acr(u32 sample_freq, u32 n, u32 cts);		int hdmi_compute_acr(u32 pclk, u32 sample_freq, u32 n, u32 cts);
	int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable);		int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable);
	int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable);		int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable);
	void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,		void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,
	struct hdmi_audio_format *aud_fmt);		struct hdmi_audio_format *aud_fmt);
	void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp,		void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp,
	struct hdmi_audio_dma *aud_dma);		struct hdmi_audio_dma *aud_dma);
			static inline bool hdmi_mode_has_audio(int mode)
			{
			return mode == HDMI_HDMI ? true : false;
			}
	#endif		#endif
	#endif		#endif

drivers/video/omap2/dss/hdmi4.c

+9 −429

Original line number	Original line	Diff line number	Diff line
	@@ -57,237 +57,6 @@ static struct {
	struct omap_dss_device output;		struct omap_dss_device output;
	} hdmi;		} hdmi;

	/*
	* Logic for the below structure :
	* user enters the CEA or VESA timings by specifying the HDMI/DVI code.
	* There is a correspondence between CEA/VESA timing and code, please
	* refer to section 6.3 in HDMI 1.3 specification for timing code.
	*
	* In the below structure, cea_vesa_timings corresponds to all OMAP4
	* supported CEA and VESA timing values.code_cea corresponds to the CEA
	* code, It is used to get the timing from cea_vesa_timing array.Similarly
	* with code_vesa. Code_index is used for back mapping, that is once EDID
	* is read from the TV, EDID is parsed to find the timing values and then
	* map it to corresponding CEA or VESA index.
	*/

	static const struct hdmi_config cea_timings[] = {
	{
	{ 640, 480, 25200, 96, 16, 48, 2, 10, 33,
	OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
	false, },
	{ 1, HDMI_HDMI },
	},
	{
	{ 720, 480, 27027, 62, 16, 60, 6, 9, 30,
	OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
	false, },
	{ 2, HDMI_HDMI },
	},
	{
	{ 1280, 720, 74250, 40, 110, 220, 5, 5, 20,
	OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
	false, },
	{ 4, HDMI_HDMI },
	},
	{
	{ 1920, 540, 74250, 44, 88, 148, 5, 2, 15,
	OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
	true, },
	{ 5, HDMI_HDMI },
	},
	{
	{ 1440, 240, 27027, 124, 38, 114, 3, 4, 15,
	OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
	true, },
	{ 6, HDMI_HDMI },
	},
	{
	{ 1920, 1080, 148500, 44, 88, 148, 5, 4, 36,
	OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
	false, },
	{ 16, HDMI_HDMI },
	},
	{
	{ 720, 576, 27000, 64, 12, 68, 5, 5, 39,
	OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
	false, },
	{ 17, HDMI_HDMI },
	},
	{
	{ 1280, 720, 74250, 40, 440, 220, 5, 5, 20,
	OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
	false, },
	{ 19, HDMI_HDMI },
	},
	{
	{ 1920, 540, 74250, 44, 528, 148, 5, 2, 15,
	OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
	true, },
	{ 20, HDMI_HDMI },
	},
	{
	{ 1440, 288, 27000, 126, 24, 138, 3, 2, 19,
	OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
	true, },
	{ 21, HDMI_HDMI },
	},
	{
	{ 1440, 576, 54000, 128, 24, 136, 5, 5, 39,
	OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
	false, },
	{ 29, HDMI_HDMI },
	},
	{
	{ 1920, 1080, 148500, 44, 528, 148, 5, 4, 36,
	OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
	false, },
	{ 31, HDMI_HDMI },
	},
	{
	{ 1920, 1080, 74250, 44, 638, 148, 5, 4, 36,
	OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
	false, },
	{ 32, HDMI_HDMI },
	},
	{
	{ 2880, 480, 108108, 248, 64, 240, 6, 9, 30,
	OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
	false, },
	{ 35, HDMI_HDMI },
	},
	{
	{ 2880, 576, 108000, 256, 48, 272, 5, 5, 39,
	OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
	false, },
	{ 37, HDMI_HDMI },
	},
	};

	static const struct hdmi_config vesa_timings[] = {
	/* VESA From Here */
	{
	{ 640, 480, 25175, 96, 16, 48, 2, 11, 31,
	OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
	false, },
	{ 4, HDMI_DVI },
	},
	{
	{ 800, 600, 40000, 128, 40, 88, 4, 1, 23,
	OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
	false, },
	{ 9, HDMI_DVI },
	},
	{
	{ 848, 480, 33750, 112, 16, 112, 8, 6, 23,
	OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
	false, },
	{ 0xE, HDMI_DVI },
	},
	{
	{ 1280, 768, 79500, 128, 64, 192, 7, 3, 20,
	OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
	false, },
	{ 0x17, HDMI_DVI },
	},
	{
	{ 1280, 800, 83500, 128, 72, 200, 6, 3, 22,
	OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
	false, },
	{ 0x1C, HDMI_DVI },
	},
	{
	{ 1360, 768, 85500, 112, 64, 256, 6, 3, 18,
	OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
	false, },
	{ 0x27, HDMI_DVI },
	},
	{
	{ 1280, 960, 108000, 112, 96, 312, 3, 1, 36,
	OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
	false, },
	{ 0x20, HDMI_DVI },
	},
	{
	{ 1280, 1024, 108000, 112, 48, 248, 3, 1, 38,
	OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
	false, },
	{ 0x23, HDMI_DVI },
	},
	{
	{ 1024, 768, 65000, 136, 24, 160, 6, 3, 29,
	OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
	false, },
	{ 0x10, HDMI_DVI },
	},
	{
	{ 1400, 1050, 121750, 144, 88, 232, 4, 3, 32,
	OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
	false, },
	{ 0x2A, HDMI_DVI },
	},
	{
	{ 1440, 900, 106500, 152, 80, 232, 6, 3, 25,
	OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
	false, },
	{ 0x2F, HDMI_DVI },
	},
	{
	{ 1680, 1050, 146250, 176 , 104, 280, 6, 3, 30,
	OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
	false, },
	{ 0x3A, HDMI_DVI },
	},
	{
	{ 1366, 768, 85500, 143, 70, 213, 3, 3, 24,
	OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
	false, },
	{ 0x51, HDMI_DVI },
	},
	{
	{ 1920, 1080, 148500, 44, 148, 80, 5, 4, 36,
	OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
	false, },
	{ 0x52, HDMI_DVI },
	},
	{
	{ 1280, 768, 68250, 32, 48, 80, 7, 3, 12,
	OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
	false, },
	{ 0x16, HDMI_DVI },
	},
	{
	{ 1400, 1050, 101000, 32, 48, 80, 4, 3, 23,
	OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
	false, },
	{ 0x29, HDMI_DVI },
	},
	{
	{ 1680, 1050, 119000, 32, 48, 80, 6, 3, 21,
	OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
	false, },
	{ 0x39, HDMI_DVI },
	},
	{
	{ 1280, 800, 79500, 32, 48, 80, 6, 3, 14,
	OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
	false, },
	{ 0x1B, HDMI_DVI },
	},
	{
	{ 1280, 720, 74250, 40, 110, 220, 5, 5, 20,
	OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
	false, },
	{ 0x55, HDMI_DVI },
	},
	{
	{ 1920, 1200, 154000, 32, 48, 80, 6, 3, 26,
	OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
	false, },
	{ 0x44, HDMI_DVI },
	},
	};

	static int hdmi_runtime_get(void)		static int hdmi_runtime_get(void)
	{		{
	int r;		int r;
	@@ -335,86 +104,6 @@ static int hdmi_init_regulator(void)
	return 0;		return 0;
	}		}

	static const struct hdmi_config *hdmi_find_timing(
	const struct hdmi_config *timings_arr,
	int len)
	{
	int i;

	for (i = 0; i < len; i++) {
	if (timings_arr[i].cm.code == hdmi.cfg.cm.code)
	return &timings_arr[i];
	}
	return NULL;
	}

	static const struct hdmi_config *hdmi_get_timings(void)
	{
	const struct hdmi_config *arr;
	int len;

	if (hdmi.cfg.cm.mode == HDMI_DVI) {
	arr = vesa_timings;
	len = ARRAY_SIZE(vesa_timings);
	} else {
	arr = cea_timings;
	len = ARRAY_SIZE(cea_timings);
	}

	return hdmi_find_timing(arr, len);
	}

	static bool hdmi_timings_compare(struct omap_video_timings *timing1,
	const struct omap_video_timings *timing2)
	{
	int timing1_vsync, timing1_hsync, timing2_vsync, timing2_hsync;

	if ((DIV_ROUND_CLOSEST(timing2->pixel_clock, 1000) ==
	DIV_ROUND_CLOSEST(timing1->pixel_clock, 1000)) &&
	(timing2->x_res == timing1->x_res) &&
	(timing2->y_res == timing1->y_res)) {

	timing2_hsync = timing2->hfp + timing2->hsw + timing2->hbp;
	timing1_hsync = timing1->hfp + timing1->hsw + timing1->hbp;
	timing2_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
	timing1_vsync = timing2->vfp + timing2->vsw + timing2->vbp;

	DSSDBG("timing1_hsync = %d timing1_vsync = %d"\
	"timing2_hsync = %d timing2_vsync = %d\n",
	timing1_hsync, timing1_vsync,
	timing2_hsync, timing2_vsync);

	if ((timing1_hsync == timing2_hsync) &&
	(timing1_vsync == timing2_vsync)) {
	return true;
	}
	}
	return false;
	}

	static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing)
	{
	int i;
	struct hdmi_cm cm = {-1};
	DSSDBG("hdmi_get_code\n");

	for (i = 0; i < ARRAY_SIZE(cea_timings); i++) {
	if (hdmi_timings_compare(timing, &cea_timings[i].timings)) {
	cm = cea_timings[i].cm;
	goto end;
	}
	}
	for (i = 0; i < ARRAY_SIZE(vesa_timings); i++) {
	if (hdmi_timings_compare(timing, &vesa_timings[i].timings)) {
	cm = vesa_timings[i].cm;
	goto end;
	}
	}

	end: return cm;

	}

	static int hdmi_power_on_core(struct omap_dss_device *dssdev)		static int hdmi_power_on_core(struct omap_dss_device *dssdev)
	{		{
	int r;		int r;
	@@ -550,7 +239,7 @@ static void hdmi_display_set_timing(struct omap_dss_device *dssdev,
	cm = hdmi_get_code(timings);		cm = hdmi_get_code(timings);
	hdmi.cfg.cm = cm;		hdmi.cfg.cm = cm;

	t = hdmi_get_timings();		t = hdmi_get_timings(cm.mode, cm.code);
	if (t != NULL) {		if (t != NULL) {
	hdmi.cfg = *t;		hdmi.cfg = *t;

	@@ -564,10 +253,11 @@ static void hdmi_display_get_timings(struct omap_dss_device *dssdev,
	struct omap_video_timings *timings)		struct omap_video_timings *timings)
	{		{
	const struct hdmi_config *cfg;		const struct hdmi_config *cfg;
			struct hdmi_cm cm = hdmi.cfg.cm;

	cfg = hdmi_get_timings();		cfg = hdmi_get_timings(cm.mode, cm.code);
	if (cfg == NULL)		if (cfg == NULL)
	cfg = &vesa_timings[0];		cfg = hdmi_default_timing();

	memcpy(timings, &cfg->timings, sizeof(cfg->timings));		memcpy(timings, &cfg->timings, sizeof(cfg->timings));
	}		}
	@@ -695,117 +385,6 @@ static int hdmi_get_clocks(struct platform_device *pdev)
	return 0;		return 0;
	}		}

	#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
	int hdmi_compute_acr(u32 sample_freq, u32 n, u32 cts)
	{
	u32 deep_color;
	bool deep_color_correct = false;
	u32 pclk = hdmi.cfg.timings.pixel_clock;

	if (n == NULL \|\| cts == NULL)
	return -EINVAL;

	/* TODO: When implemented, query deep color mode here. */
	deep_color = 100;

	/*
	* When using deep color, the default N value (as in the HDMI
	* specification) yields to an non-integer CTS. Hence, we
	* modify it while keeping the restrictions described in
	* section 7.2.1 of the HDMI 1.4a specification.
	*/
	switch (sample_freq) {
	case 32000:
	case 48000:
	case 96000:
	case 192000:
	if (deep_color == 125)
	if (pclk == 27027 \|\| pclk == 74250)
	deep_color_correct = true;
	if (deep_color == 150)
	if (pclk == 27027)
	deep_color_correct = true;
	break;
	case 44100:
	case 88200:
	case 176400:
	if (deep_color == 125)
	if (pclk == 27027)
	deep_color_correct = true;
	break;
	default:
	return -EINVAL;
	}

	if (deep_color_correct) {
	switch (sample_freq) {
	case 32000:
	*n = 8192;
	break;
	case 44100:
	*n = 12544;
	break;
	case 48000:
	*n = 8192;
	break;
	case 88200:
	*n = 25088;
	break;
	case 96000:
	*n = 16384;
	break;
	case 176400:
	*n = 50176;
	break;
	case 192000:
	*n = 32768;
	break;
	default:
	return -EINVAL;
	}
	} else {
	switch (sample_freq) {
	case 32000:
	*n = 4096;
	break;
	case 44100:
	*n = 6272;
	break;
	case 48000:
	*n = 6144;
	break;
	case 88200:
	*n = 12544;
	break;
	case 96000:
	*n = 12288;
	break;
	case 176400:
	*n = 25088;
	break;
	case 192000:
	*n = 24576;
	break;
	default:
	return -EINVAL;
	}
	}
	/* Calculate CTS. See HDMI 1.3a or 1.4a specifications */
	cts = pclk (n / 128) deep_color / (sample_freq / 10);

	return 0;
	}

	static bool hdmi_mode_has_audio(void)
	{
	if (hdmi.cfg.cm.mode == HDMI_HDMI)
	return true;
	else
	return false;
	}

	#endif

	static int hdmi_connect(struct omap_dss_device *dssdev,		static int hdmi_connect(struct omap_dss_device *dssdev,
	struct omap_dss_device *dst)		struct omap_dss_device *dst)
	{		{
	@@ -878,7 +457,7 @@ static int hdmi_audio_enable(struct omap_dss_device *dssdev)

	mutex_lock(&hdmi.lock);		mutex_lock(&hdmi.lock);

	if (!hdmi_mode_has_audio()) {		if (!hdmi_mode_has_audio(hdmi.cfg.cm.mode)) {
	r = -EPERM;		r = -EPERM;
	goto err;		goto err;
	}		}
	@@ -916,7 +495,7 @@ static bool hdmi_audio_supported(struct omap_dss_device *dssdev)

	mutex_lock(&hdmi.lock);		mutex_lock(&hdmi.lock);

	r = hdmi_mode_has_audio();		r = hdmi_mode_has_audio(hdmi.cfg.cm.mode);

	mutex_unlock(&hdmi.lock);		mutex_unlock(&hdmi.lock);
	return r;		return r;
	@@ -926,15 +505,16 @@ static int hdmi_audio_config(struct omap_dss_device *dssdev,
	struct omap_dss_audio *audio)		struct omap_dss_audio *audio)
	{		{
	int r;		int r;
			u32 pclk = hdmi.cfg.timings.pixel_clock;

	mutex_lock(&hdmi.lock);		mutex_lock(&hdmi.lock);

	if (!hdmi_mode_has_audio()) {		if (!hdmi_mode_has_audio(hdmi.cfg.cm.mode)) {
	r = -EPERM;		r = -EPERM;
	goto err;		goto err;
	}		}

	r = hdmi4_audio_config(&hdmi.core, &hdmi.wp, audio);		r = hdmi4_audio_config(&hdmi.core, &hdmi.wp, audio, pclk);
	if (r)		if (r)
	goto err;		goto err;

drivers/video/omap2/dss/hdmi4_core.c

+2 −2

Original line number	Original line	Diff line number	Diff line
	@@ -789,7 +789,7 @@ static void hdmi_core_audio_infoframe_cfg(struct hdmi_core_data *core,
	}		}

	int hdmi4_audio_config(struct hdmi_core_data core, struct hdmi_wp_data wp,		int hdmi4_audio_config(struct hdmi_core_data core, struct hdmi_wp_data wp,
	struct omap_dss_audio *audio)		struct omap_dss_audio *audio, u32 pclk)
	{		{
	struct hdmi_audio_format audio_format;		struct hdmi_audio_format audio_format;
	struct hdmi_audio_dma audio_dma;		struct hdmi_audio_dma audio_dma;
	@@ -856,7 +856,7 @@ int hdmi4_audio_config(struct hdmi_core_data core, struct hdmi_wp_data wp,
	return -EINVAL;		return -EINVAL;
	}		}

	err = hdmi_compute_acr(fs_nr, &n, &cts);		err = hdmi_compute_acr(pclk, fs_nr, &n, &cts);

	/* Audio clock regeneration settings */		/* Audio clock regeneration settings */
	acore.n = n;		acore.n = n;

drivers/video/omap2/dss/hdmi4_core.h

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -269,7 +269,7 @@ int hdmi4_core_init(struct platform_device pdev, struct hdmi_core_data core);
	int hdmi4_audio_start(struct hdmi_core_data core, struct hdmi_wp_data wp);		int hdmi4_audio_start(struct hdmi_core_data core, struct hdmi_wp_data wp);
	void hdmi4_audio_stop(struct hdmi_core_data core, struct hdmi_wp_data wp);		void hdmi4_audio_stop(struct hdmi_core_data core, struct hdmi_wp_data wp);
	int hdmi4_audio_config(struct hdmi_core_data core, struct hdmi_wp_data wp,		int hdmi4_audio_config(struct hdmi_core_data core, struct hdmi_wp_data wp,
	struct omap_dss_audio *audio);		struct omap_dss_audio *audio, u32 pclk);
	int hdmi4_audio_get_dma_port(u32 offset, u32 size);		int hdmi4_audio_get_dma_port(u32 offset, u32 size);
	#endif		#endif

Original line number	Original line	Diff line number	Diff line
	@@ -269,7 +269,7 @@ int hdmi4_core_init(struct platform_device pdev, struct hdmi_core_data core);
	int hdmi4_audio_start(struct hdmi_core_data core, struct hdmi_wp_data wp);		int hdmi4_audio_start(struct hdmi_core_data core, struct hdmi_wp_data wp);
	void hdmi4_audio_stop(struct hdmi_core_data core, struct hdmi_wp_data wp);		void hdmi4_audio_stop(struct hdmi_core_data core, struct hdmi_wp_data wp);
	int hdmi4_audio_config(struct hdmi_core_data core, struct hdmi_wp_data wp,		int hdmi4_audio_config(struct hdmi_core_data core, struct hdmi_wp_data wp,
	struct omap_dss_audio *audio);		struct omap_dss_audio *audio, u32 pclk);
	int hdmi4_audio_get_dma_port(u32 offset, u32 size);		int hdmi4_audio_get_dma_port(u32 offset, u32 size);
	#endif		#endif