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Commit 08b25963 authored by Yazen Ghannam's avatar Yazen Ghannam Committed by Ingo Molnar
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x86/CPU/AMD: Fix Zen SMT topology 



After:

  a33d3317 ("x86/CPU/AMD: Fix Bulldozer topology")

our  SMT scheduling topology for Fam17h systems is broken, because
the ThreadId is included in the ApicId when SMT is enabled.

So, without further decoding cpu_core_id is unique for each thread
rather than the same for threads on the same core. This didn't affect
systems with SMT disabled. Make cpu_core_id be what it is defined to be.

Signed-off-by: default avatarYazen Ghannam <Yazen.Ghannam@amd.com>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Cc: <stable@vger.kernel.org> # 4.9
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/20170205105022.8705-2-bp@alien8.de


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent 79a8b9aa

arch/x86/kernel/cpu/amd.c

+7 −0
Original line number Diff line number Diff line
@@ -319,6 +319,13 @@ static void amd_get_topology(struct cpuinfo_x86 *c) 
		if (c->x86 == 0x15)

			c->cu_id = ebx & 0xff;



		if (c->x86 >= 0x17) {

			c->cpu_core_id = ebx & 0xff;



			if (smp_num_siblings > 1)

				c->x86_max_cores /= smp_num_siblings;

		}



		/*

		 * We may have multiple LLCs if L3 caches exist, so check if we

		 * have an L3 cache by looking at the L3 cache CPUID leaf.