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Commit 08af8310 authored by Kevin Hilman's avatar Kevin Hilman
Browse files

Merge tag 'meson-clk-headers-5.2' of git://github.com/BayLibre/clk-meson into v5.2/dt64 

- Adds VPU and Video Decoder clocks IDs on Meson8b
- Finally remove the wrong ABP Meson8b clock id
- Adds Video Decoder, PCIe PLL & CPU Clock IDs on G12A
- Re-expose SAR_ADC_SEL and CTS_OSCIN on G12A AO clock controller
- Unexpose some AXG-Audio input clocks IDs

* tag 'meson-clk-headers-5.2' of git://github.com/BayLibre/clk-meson:
  dt-bindings: clock: meson8b: export the video decoder clocks
  dt-bindings: clock: meson8b: export the VPU clock
  dt-bindings: clock: g12a-aoclk: expose CLKID_AO_CTS_OSCIN
  dt-bindings: clock: meson8b: drop the "ABP" clock definition
  dt-bindings: clk: g12a-clkc: add VDEC clock IDs
  dt-bindings: clock: axg-audio: unexpose controller inputs
  dt-bindings: clk: g12a-clkc: add PCIE PLL clock ID
  clk: g12a-aoclk: re-export CLKID_AO_SAR_ADC_SEL clock id
  clk: meson-g12a: add cpu clock bindings
parents 55d76e83 77a725ff

drivers/clk/meson/axg-audio.h

+20 −0
Original line number Diff line number Diff line
@@ -60,6 +60,26 @@ 
#define AUD_CLKID_MST5			6

#define AUD_CLKID_MST6			7

#define AUD_CLKID_MST7			8

#define AUD_CLKID_SLV_SCLK0		9

#define AUD_CLKID_SLV_SCLK1		10

#define AUD_CLKID_SLV_SCLK2		11

#define AUD_CLKID_SLV_SCLK3		12

#define AUD_CLKID_SLV_SCLK4		13

#define AUD_CLKID_SLV_SCLK5		14

#define AUD_CLKID_SLV_SCLK6		15

#define AUD_CLKID_SLV_SCLK7		16

#define AUD_CLKID_SLV_SCLK8		17

#define AUD_CLKID_SLV_SCLK9		18

#define AUD_CLKID_SLV_LRCLK0		19

#define AUD_CLKID_SLV_LRCLK1		20

#define AUD_CLKID_SLV_LRCLK2		21

#define AUD_CLKID_SLV_LRCLK3		22

#define AUD_CLKID_SLV_LRCLK4		23

#define AUD_CLKID_SLV_LRCLK5		24

#define AUD_CLKID_SLV_LRCLK6		25

#define AUD_CLKID_SLV_LRCLK7		26

#define AUD_CLKID_SLV_LRCLK8		27

#define AUD_CLKID_SLV_LRCLK9		28

#define AUD_CLKID_MST_A_MCLK_SEL	59

#define AUD_CLKID_MST_B_MCLK_SEL	60

#define AUD_CLKID_MST_C_MCLK_SEL	61

drivers/clk/meson/g12a-aoclk.h

+0 −2
Original line number Diff line number Diff line
@@ -16,9 +16,7 @@ 
 * to expose, such as the internal muxes and dividers of composite clocks,

 * will remain defined here.

 */

#define CLKID_AO_SAR_ADC_SEL	16

#define CLKID_AO_SAR_ADC_DIV	17

#define CLKID_AO_CTS_OSCIN	19

#define CLKID_AO_32K_PRE	20

#define CLKID_AO_32K_DIV	21

#define CLKID_AO_32K_SEL	22

include/dt-bindings/clock/axg-audio-clkc.h

+0 −20
Original line number Diff line number Diff line
@@ -7,26 +7,6 @@ 
#ifndef __AXG_AUDIO_CLKC_BINDINGS_H

#define __AXG_AUDIO_CLKC_BINDINGS_H



#define AUD_CLKID_SLV_SCLK0		9

#define AUD_CLKID_SLV_SCLK1		10

#define AUD_CLKID_SLV_SCLK2		11

#define AUD_CLKID_SLV_SCLK3		12

#define AUD_CLKID_SLV_SCLK4		13

#define AUD_CLKID_SLV_SCLK5		14

#define AUD_CLKID_SLV_SCLK6		15

#define AUD_CLKID_SLV_SCLK7		16

#define AUD_CLKID_SLV_SCLK8		17

#define AUD_CLKID_SLV_SCLK9		18

#define AUD_CLKID_SLV_LRCLK0		19

#define AUD_CLKID_SLV_LRCLK1		20

#define AUD_CLKID_SLV_LRCLK2		21

#define AUD_CLKID_SLV_LRCLK3		22

#define AUD_CLKID_SLV_LRCLK4		23

#define AUD_CLKID_SLV_LRCLK5		24

#define AUD_CLKID_SLV_LRCLK6		25

#define AUD_CLKID_SLV_LRCLK7		26

#define AUD_CLKID_SLV_LRCLK8		27

#define AUD_CLKID_SLV_LRCLK9		28

#define AUD_CLKID_DDR_ARB		29

#define AUD_CLKID_PDM			30

#define AUD_CLKID_TDMIN_A		31

include/dt-bindings/clock/g12a-aoclkc.h

+2 −0
Original line number Diff line number Diff line
@@ -26,7 +26,9 @@ 
#define CLKID_AO_M4_FCLK	13

#define CLKID_AO_M4_HCLK	14

#define CLKID_AO_CLK81		15

#define CLKID_AO_SAR_ADC_SEL	16

#define CLKID_AO_SAR_ADC_CLK	18

#define CLKID_AO_CTS_OSCIN	19

#define CLKID_AO_32K		23

#define CLKID_AO_CEC		27

#define CLKID_AO_CTS_RTC_OSCIN	28

include/dt-bindings/clock/g12a-clkc.h

+5 −0
Original line number Diff line number Diff line
@@ -131,5 +131,10 @@ 
#define CLKID_MALI_1				174

#define CLKID_MALI				175

#define CLKID_MPLL_5OM				177

#define CLKID_CPU_CLK				187

#define CLKID_PCIE_PLL				201

#define CLKID_VDEC_1				204

#define CLKID_VDEC_HEVC				207

#define CLKID_VDEC_HEVCF			210



#endif /* __G12A_CLKC_H */