Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 084e5bb1 authored by Kavya Sree Kotagiri's avatar Kavya Sree Kotagiri Committed by David S. Miller
Browse files

net: mscc: Enable all ports in QSGMII 



When Ocelot phy-mode is QSGMII, all 4 ports involved in
QSGMII shall be kept out of reset and
Tx lanes shall be enabled to pass the data.

Fixes: a556c76a ("net: mscc: Add initial Ocelot switch support")
Signed-off-by: default avatarKavya Sree Kotagiri <kavyasree.kotagiri@microchip.com>
Signed-off-by: default avatarSteen Hegelund <Steen.Hegelund@microchip.com>
Co-developed-by: default avatarSteen Hegelund <Steen.Hegelund@microchip.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 46b1c18f

drivers/net/ethernet/mscc/ocelot_board.c

+11 −3
Original line number Diff line number Diff line
@@ -267,6 +267,7 @@ static int mscc_ocelot_probe(struct platform_device *pdev) 
		struct phy *serdes;

		void __iomem *regs;

		char res_name[8];

		int phy_mode;

		u32 port;



		if (of_property_read_u32(portnp, "reg", &port))
@@ -292,11 +293,11 @@ static int mscc_ocelot_probe(struct platform_device *pdev) 
		if (err)

			return err;



		err = of_get_phy_mode(portnp);

		if (err < 0)

		phy_mode = of_get_phy_mode(portnp);

		if (phy_mode < 0)

			ocelot->ports[port]->phy_mode = PHY_INTERFACE_MODE_NA;

		else

			ocelot->ports[port]->phy_mode = err;

			ocelot->ports[port]->phy_mode = phy_mode;



		switch (ocelot->ports[port]->phy_mode) {

		case PHY_INTERFACE_MODE_NA:
@@ -304,6 +305,13 @@ static int mscc_ocelot_probe(struct platform_device *pdev) 
		case PHY_INTERFACE_MODE_SGMII:

			break;

		case PHY_INTERFACE_MODE_QSGMII:

			/* Ensure clock signals and speed is set on all

			 * QSGMII links

			 */

			ocelot_port_writel(ocelot->ports[port],

					   DEV_CLOCK_CFG_LINK_SPEED

					   (OCELOT_SPEED_1000),

					   DEV_CLOCK_CFG);

			break;

		default:

			dev_err(ocelot->dev,