Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 0815d774 authored by Jordan Crouse's avatar Jordan Crouse Committed by Rob Clark
Browse files

drm/msm: Add a name field for gem objects 



For debugging purposes it is useful to assign descriptions
to buffers so that we know what they are used for. Add
a field to the buffer object and use that to name the various
kernel side allocations which ends up looking like like this
in /d/dri/X/gem:

   flags       id ref  offset   kaddr            size     madv      name
   00040000: I  0 ( 1) 00000000 0000000070b79eca 00004096           memptrs
      vmas: [gpu: 01000000,mapped,inuse=1]
   00020000: I  0 ( 1) 00000000 0000000031ed4074 00032768           ring0

Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
parent 7ad0e8cf

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

+8 −0
Original line number Diff line number Diff line
@@ -510,6 +510,7 @@ static int a5xx_ucode_init(struct msm_gpu *gpu) 
		a5xx_gpu->pm4_bo = adreno_fw_create_bo(gpu,

			adreno_gpu->fw[ADRENO_FW_PM4], &a5xx_gpu->pm4_iova);





		if (IS_ERR(a5xx_gpu->pm4_bo)) {

			ret = PTR_ERR(a5xx_gpu->pm4_bo);

			a5xx_gpu->pm4_bo = NULL;
@@ -517,6 +518,8 @@ static int a5xx_ucode_init(struct msm_gpu *gpu) 
				ret);

			return ret;

		}



		msm_gem_object_set_name(a5xx_gpu->pm4_bo, "pm4fw");

	}



	if (!a5xx_gpu->pfp_bo) {
@@ -530,6 +533,8 @@ static int a5xx_ucode_init(struct msm_gpu *gpu) 
				ret);

			return ret;

		}



		msm_gem_object_set_name(a5xx_gpu->pfp_bo, "pfpfw");

	}



	gpu_write64(gpu, REG_A5XX_CP_ME_INSTR_BASE_LO,
@@ -1214,6 +1219,9 @@ static int a5xx_crashdumper_init(struct msm_gpu *gpu, 
		SZ_1M, MSM_BO_UNCACHED, gpu->aspace,

		&dumper->bo, &dumper->iova);



	if (!IS_ERR(dumper->ptr))

		msm_gem_object_set_name(dumper->bo, "crashdump");



	return PTR_ERR_OR_ZERO(dumper->ptr);

}

drivers/gpu/drm/msm/adreno/a5xx_power.c

+2 −0
Original line number Diff line number Diff line
@@ -300,6 +300,8 @@ void a5xx_gpmu_ucode_init(struct msm_gpu *gpu) 
	if (IS_ERR(ptr))

		return;



	msm_gem_object_set_name(a5xx_gpu->gpmu_bo, "gpmufw");



	while (cmds_size > 0) {

		int i;

		uint32_t _size = cmds_size > TYPE4_MAX_PAYLOAD ?

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

+2 −0
Original line number Diff line number Diff line
@@ -245,6 +245,8 @@ static int preempt_init_ring(struct a5xx_gpu *a5xx_gpu, 
	if (IS_ERR(ptr))

		return PTR_ERR(ptr);



	msm_gem_object_set_name(bo, "preempt");



	a5xx_gpu->preempt_bo[ring->id] = bo;

	a5xx_gpu->preempt_iova[ring->id] = iova;

	a5xx_gpu->preempt[ring->id] = ptr;

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

+2 −0
Original line number Diff line number Diff line
@@ -333,6 +333,8 @@ static int a6xx_ucode_init(struct msm_gpu *gpu) 


			return ret;

		}



		msm_gem_object_set_name(a6xx_gpu->sqe_bo, "sqefw");

	}



	gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE_LO,

drivers/gpu/drm/msm/dsi/dsi_host.c

+2 −0
Original line number Diff line number Diff line
@@ -1083,6 +1083,8 @@ int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size) 
		return PTR_ERR(data);

	}



	msm_gem_object_set_name(msm_host->tx_gem_obj, "tx_gem");



	msm_host->tx_size = msm_host->tx_gem_obj->size;



	return 0;