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Commit 077410c7 authored by Shyam Sundar S K's avatar Shyam Sundar S K Committed by Greg Kroah-Hartman
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net: amd-xgbe: Toggle PLL settings during rate change 



[ Upstream commit daf182d360e509a494db18666799f4e85d83dda0 ]

For each rate change command submission, the FW has to do a phy
power off sequence internally. For this to happen correctly, the
PLL re-initialization control setting has to be turned off before
sending mailbox commands and re-enabled once the command submission
is complete.

Without the PLL control setting, the link up takes longer time in a
fixed phy configuration.

Fixes: 47f164de ("amd-xgbe: Add PCI device support")
Co-developed-by: default avatarSudheesh Mavila <sudheesh.mavila@amd.com>
Signed-off-by: default avatarSudheesh Mavila <sudheesh.mavila@amd.com>
Signed-off-by: default avatarShyam Sundar S K <Shyam-sundar.S-k@amd.com>
Acked-by: default avatarTom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 63a3b1af

drivers/net/ethernet/amd/xgbe/xgbe-common.h

+8 −0
Original line number Diff line number Diff line
@@ -1331,6 +1331,10 @@ 
#define MDIO_VEND2_PMA_CDR_CONTROL	0x8056

#endif



#ifndef MDIO_VEND2_PMA_MISC_CTRL0

#define MDIO_VEND2_PMA_MISC_CTRL0	0x8090

#endif



#ifndef MDIO_CTRL1_SPEED1G

#define MDIO_CTRL1_SPEED1G		(MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100)

#endif
@@ -1389,6 +1393,10 @@ 
#define XGBE_PMA_RX_RST_0_RESET_ON	0x10

#define XGBE_PMA_RX_RST_0_RESET_OFF	0x00



#define XGBE_PMA_PLL_CTRL_MASK		BIT(15)

#define XGBE_PMA_PLL_CTRL_ENABLE	BIT(15)

#define XGBE_PMA_PLL_CTRL_DISABLE	0x0000



/* Bit setting and getting macros

 *  The get macro will extract the current bit field value from within

 *  the variable

drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c

+19 −1
Original line number Diff line number Diff line
@@ -1972,12 +1972,26 @@ static void xgbe_phy_rx_reset(struct xgbe_prv_data *pdata) 
	}

}



static void xgbe_phy_pll_ctrl(struct xgbe_prv_data *pdata, bool enable)

{

	XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0,

			 XGBE_PMA_PLL_CTRL_MASK,

			 enable ? XGBE_PMA_PLL_CTRL_ENABLE

				: XGBE_PMA_PLL_CTRL_DISABLE);



	/* Wait for command to complete */

	usleep_range(100, 200);

}



static void xgbe_phy_perform_ratechange(struct xgbe_prv_data *pdata,

					unsigned int cmd, unsigned int sub_cmd)

{

	unsigned int s0 = 0;

	unsigned int wait;



	/* Disable PLL re-initialization during FW command processing */

	xgbe_phy_pll_ctrl(pdata, false);



	/* Log if a previous command did not complete */

	if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) {

		netif_dbg(pdata, link, pdata->netdev,
@@ -1998,7 +2012,7 @@ static void xgbe_phy_perform_ratechange(struct xgbe_prv_data *pdata, 
	wait = XGBE_RATECHANGE_COUNT;

	while (wait--) {

		if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))

			return;

			goto reenable_pll;



		usleep_range(1000, 2000);

	}
@@ -2008,6 +2022,10 @@ static void xgbe_phy_perform_ratechange(struct xgbe_prv_data *pdata, 


	/* Reset on error */

	xgbe_phy_rx_reset(pdata);



reenable_pll:

	/* Enable PLL re-initialization */

	xgbe_phy_pll_ctrl(pdata, true);

}



static void xgbe_phy_rrc(struct xgbe_prv_data *pdata)