Merge branch 'pwm-dmtimer-fixes' into omap-for-v5.0/fixes-v2 (072167d1) · Commits · e / devices / android_kernel_fairphone_FP5

arch/arm/boot/dts/omap4-droid4-xt894.dts

+11 −0

Original line number	Diff line number	Diff line
		@@ -644,6 +644,17 @@
		};
		};

		/* Configure pwm clock source for timers 8 & 9 */
		&timer8 {
		assigned-clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>;
		assigned-clock-parents = <&sys_clkin_ck>;
		};

		&timer9 {
		assigned-clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>;
		assigned-clock-parents = <&sys_clkin_ck>;
		};

		/*
		* As uart1 is wired to mdm6600 with rts and cts, we can use the cts pin for
		* uart1 wakeirq.

+3 −3

Original line number	Diff line number	Diff line
		@@ -781,12 +781,12 @@ static const struct sysc_revision_quirk sysc_revision_quirks[] = {
		SYSC_QUIRK("smartreflex", 0, -1, 0x38, -1, 0x00000000, 0xffffffff,
		SYSC_QUIRK_LEGACY_IDLE),
		SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff,
		SYSC_QUIRK_LEGACY_IDLE),
		0),
		/* Some timers on omap4 and later */
		SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x50002100, 0xffffffff,
		SYSC_QUIRK_LEGACY_IDLE),
		0),
		SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x4fff1301, 0xffff00ff,
		SYSC_QUIRK_LEGACY_IDLE),
		0),
		SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff,
		SYSC_QUIRK_LEGACY_IDLE),
		/* Uarts on omap4 and later */

+4 −1

Original line number	Diff line number	Diff line
		@@ -154,6 +154,10 @@ static int omap_dm_timer_of_set_source(struct omap_dm_timer *timer)
		if (IS_ERR(parent))
		return -ENODEV;

		/* Bail out if both clocks point to fck */
		if (clk_is_match(parent, timer->fclk))
		return 0;

		ret = clk_set_parent(timer->fclk, parent);
		if (ret < 0)
		pr_err("%s: failed to set parent\n", __func__);
		@@ -864,7 +868,6 @@ static int omap_dm_timer_probe(struct platform_device *pdev)
		timer->pdev = pdev;

		pm_runtime_enable(dev);
		pm_runtime_irq_safe(dev);

		if (!timer->reserved) {
		ret = pm_runtime_get_sync(dev);