Merge tag 'gpio-v4.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio

In our Bluetooth example the "reset-gpios" refers to the second GpioIo()

resource, second pin in that resource with the GPIO number of 31.

It is possible to leave holes in the array of GPIOs. This is useful in

cases like with SPI host controllers where some chip selects may be

implemented as GPIOs and some as native signals. For example a SPI host

controller can have chip selects 0 and 2 implemented as GPIOs and 1 as

native:

  Package () {

      "cs-gpios",

      Package () {

          ^GPIO, 19, 0, 0, // chip select 0: GPIO

          0,               // chip select 1: native signal

          ^GPIO, 20, 0, 0, // chip select 2: GPIO

      }

  }

Other supported properties

--------------------------

Following Device Tree compatible device properties are also supported by

_DSD device properties for GPIO controllers:

- gpio-hog

- output-high

- output-low

- input

- line-name

Example:

  Name (_DSD, Package () {

      // _DSD Hierarchical Properties Extension UUID

      ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),

      Package () {

          Package () {"hog-gpio8", "G8PU"}

      }

  })

  Name (G8PU, Package () {

      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),

      Package () {

          Package () {"gpio-hog", 1},

          Package () {"gpios", Package () {8, 0}},

          Package () {"output-high", 1},

          Package () {"line-name", "gpio8-pullup"},

      }

  })

- gpio-line-names

Example:

  Package () {

      "gpio-line-names",

      Package () {

          "SPI0_CS_N", "EXP2_INT", "MUX6_IO", "UART0_RXD", "MUX7_IO",

          "LVL_C_A1", "MUX0_IO", "SPI1_MISO"

      }

  }

See Documentation/devicetree/bindings/gpio/gpio.txt for more information

about these properties.

ACPI GPIO Mappings Provided by Drivers

--------------------------------------

SEMTECH SX150x GPIO expander bindings

Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and

../interrupt-controller/interrupts.txt for generic information regarding

pin controller, GPIO, and interrupt bindings.

Required properties:

- compatible: should be "semtech,sx1506q",

- compatible: should be one of :

			"semtech,sx1506q",

			"semtech,sx1508q",

			"semtech,sx1509q",

			"semtech,sx1502q".

- reg: The I2C slave address for this device.

- interrupt-parent: phandle of the parent interrupt controller.

- interrupts: Interrupt specifier for the controllers interrupt.

- #gpio-cells: Should be 2. The first cell is the GPIO number and the

		second cell is used to specify optional parameters:

		bit 0: polarity (0: normal, 1: inverted)

- gpio-controller: Marks the device as a GPIO controller.

Optional properties :

- interrupt-parent: phandle of the parent interrupt controller.

- interrupts: Interrupt specifier for the controllers interrupt.

- interrupt-controller: Marks the device as a interrupt controller.

- semtech,probe-reset: Will trigger a reset of the GPIO expander on probe,

		only for sx1508q and sx1509q

The GPIO expander can optionally be used as an interrupt controller, in

which case it uses the default two cell specifier as described in

Documentation/devicetree/bindings/interrupt-controller/interrupts.txt.

which case it uses the default two cell specifier.

Required properties for pin configuration sub-nodes:

 - pins: List of pins to which the configuration applies.

Optional properties for pin configuration sub-nodes:

----------------------------------------------------

 - bias-disable: disable any pin bias, except the OSCIO pin

 - bias-pull-up: pull up the pin, except the OSCIO pin

 - bias-pull-down: pull down the pin, except the OSCIO pin

 - bias-pull-pin-default: use pin-default pull state, except the OSCIO pin

 - drive-push-pull: drive actively high and low

 - drive-open-drain: drive with open drain only for sx1508q and sx1509q and except the OSCIO pin

 - output-low: set the pin to output mode with low level

 - output-high: set the pin to output mode with high level

Example:

	i2c_gpio_expander@20{

	i2c0gpio-expander@20{

		#gpio-cells = <2>;

		#interrupt-cells = <2>;

		compatible = "semtech,sx1506q";

		gpio-controller;

		interrupt-controller;

		pinctrl-names = "default";

		pinctrl-0 = <&gpio1_cfg_pins>;

		gpio1_cfg_pins: gpio1-cfg {

			pins = "gpio1";

			bias-pull-up;

		};

	};

the header <linux/irq.h>. So basically such a driver is utilizing two sub-

systems simultaneously: gpio and irq.

RT_FULL: GPIO driver should not use spinlock_t or any sleepable APIs

(like PM runtime) as part of its irq_chip implementation on -RT.

RT_FULL: a realtime compliant GPIO driver should not use spinlock_t or any

sleepable APIs (like PM runtime) as part of its irq_chip implementation.

- spinlock_t should be replaced with raw_spinlock_t [1].

- If sleepable APIs have to be used, these can be done from the .irq_bus_lock()

  and .irq_bus_unlock() callbacks, as these are the only slowpath callbacks

GPIO irqchips usually fall in one of two categories:

* CHAINED GPIO irqchips: these are usually the type that is embedded on

  an SoC. This means that there is a fast IRQ handler for the GPIOs that

  an SoC. This means that there is a fast IRQ flow handler for the GPIOs that

  gets called in a chain from the parent IRQ handler, most typically the

  system interrupt controller. This means the GPIO irqchip is registered

  using irq_set_chained_handler() or the corresponding

  gpiochip_set_chained_irqchip() helper function, and the GPIO irqchip

  handler will be called immediately from the parent irqchip, while

  holding the IRQs disabled. The GPIO irqchip will then end up calling

  something like this sequence in its interrupt handler:

  static irqreturn_t tc3589x_gpio_irq(int irq, void *data)

  system interrupt controller. This means that the GPIO irqchip handler will

  be called immediately from the parent irqchip, while holding the IRQs

  disabled. The GPIO irqchip will then end up calling something like this

  sequence in its interrupt handler:

  static irqreturn_t foo_gpio_irq(int irq, void *data)

      chained_irq_enter(...);

      generic_handle_irq(...);

      chained_irq_exit(...);

  Chained GPIO irqchips typically can NOT set the .can_sleep flag on

  struct gpio_chip, as everything happens directly in the callbacks.

  struct gpio_chip, as everything happens directly in the callbacks: no

  slow bus traffic like I2C can be used.

  RT_FULL: Note, chained IRQ handlers will not be forced threaded on -RT.

  As result, spinlock_t or any sleepable APIs (like PM runtime) can't be used

  in chained IRQ handler.

  if required (and if it can't be converted to the nested threaded GPIO irqchip)

  - chained IRQ handler can be converted to generic irq handler and this way

  it will be threaded IRQ handler on -RT and hard IRQ handler on non-RT

  If required (and if it can't be converted to the nested threaded GPIO irqchip)

  a chained IRQ handler can be converted to generic irq handler and this way

  it will be a threaded IRQ handler on -RT and a hard IRQ handler on non-RT

  (for example, see [3]).

  Know W/A: The generic_handle_irq() is expected to be called with IRQ disabled,

  so IRQ core will complain if it will be called from IRQ handler which is

  forced thread. The "fake?" raw lock can be used to W/A this problem:

  so the IRQ core will complain if it is called from an IRQ handler which is

  forced to a thread. The "fake?" raw lock can be used to W/A this problem:

	raw_spinlock_t wa_lock;

	static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)

  by the driver. The hallmark of this driver is to call something like

  this in its interrupt handler:

  static irqreturn_t tc3589x_gpio_irq(int irq, void *data)

  static irqreturn_t foo_gpio_irq(int irq, void *data)

      ...

      handle_nested_irq(irq);

some helpers that can be enabled by selecting the GPIOLIB_IRQCHIP Kconfig

symbol:

* gpiochip_irqchip_add(): adds an irqchip to a gpiochip. It will pass

* gpiochip_irqchip_add(): adds a chained irqchip to a gpiochip. It will pass

  the struct gpio_chip* for the chip to all IRQ callbacks, so the callbacks

  need to embed the gpio_chip in its state container and obtain a pointer

  to the container using container_of().

  (See Documentation/driver-model/design-patterns.txt)

  If there is a need to exclude certain GPIOs from the IRQ domain, one can

  set .irq_need_valid_mask of the gpiochip before gpiochip_add_data() is

  called. This allocates .irq_valid_mask with as many bits set as there are

  GPIOs in the chip. Drivers can exclude GPIOs by clearing bits from this

  mask. The mask must be filled in before gpiochip_irqchip_add() is called.

* gpiochip_irqchip_add_nested(): adds a nested irqchip to a gpiochip.

  Apart from that it works exactly like the chained irqchip.

* gpiochip_set_chained_irqchip(): sets up a chained irq handler for a

  gpio_chip from a parent IRQ and passes the struct gpio_chip* as handler

  data. (Notice handler data, since the irqchip data is likely used by the

  parent irqchip!) This is for the chained type of chip. This is also used

  to set up a nested irqchip if NULL is passed as handler.

  parent irqchip!).

* gpiochip_set_nested_irqchip(): sets up a nested irq handler for a

  gpio_chip from a parent IRQ. As the parent IRQ has usually been

  explicitly requested by the driver, this does very little more than

  mark all the child IRQs as having the other IRQ as parent.

If there is a need to exclude certain GPIOs from the IRQ domain, you can

set .irq_need_valid_mask of the gpiochip before gpiochip_add_data() is

called. This allocates an .irq_valid_mask with as many bits set as there

are GPIOs in the chip. Drivers can exclude GPIOs by clearing bits from this

mask. The mask must be filled in before gpiochip_irqchip_add() or

gpiochip_irqchip_add_nested() is called.

To use the helpers please keep the following in mind:

typically be called in the .startup() and .shutdown() callbacks from the

irqchip.

When using the gpiolib irqchip helpers, these callback are automatically

assigned.

Real-Time compliance for GPIO IRQ chips

---------------------------------------

#include <linux/amba/bus.h>

#include <linux/amba/clcd.h>

#include <linux/amba/mmci.h>

#include <linux/amba/pl061.h>

#include <linux/io.h>

#include <linux/platform_data/clk-integrator.h>

#include <linux/slab.h>

config GPIO_EM

	tristate "Emma Mobile GPIO"

	depends on ARM && OF_GPIO

	depends on (ARCH_EMEV2 || COMPILE_TEST) && OF_GPIO

	help

	  Say yes here to support GPIO on Renesas Emma Mobile SoCs.

config GPIO_VX855

	tristate "VIA VX855/VX875 GPIO"

	depends on PCI

	depends on (X86 || COMPILE_TEST) && PCI

	select MFD_CORE

	select MFD_VX855

	help

config GPIO_ZX

	bool "ZTE ZX GPIO support"

	depends on ARCH_ZX || COMPILE_TEST

	select GPIOLIB_IRQCHIP

	help

	  Say yes here to support the GPIO device on ZTE ZX SoCs.

config GPIO_SCH

	tristate "Intel SCH/TunnelCreek/Centerton/Quark X1000 GPIO"

	depends on PCI

	depends on (X86 || COMPILE_TEST) && PCI

	select MFD_CORE

	select LPC_SCH

	help

	  platform-neutral GPIO calls.

config GPIO_SX150X

	bool "Semtech SX150x I2C GPIO expander"

	depends on I2C=y

	select GPIOLIB_IRQCHIP

	bool "Semtech SX150x I2C GPIO expander (deprecated)"

	depends on PINCTRL && I2C=y

	select PINCTRL_SX150X

	default n

	help

	  Say yes here to provide support for Semtech SX150-series I2C

	  GPIO expanders. Compatible models include:

	  8 bits:  sx1508q

	  16 bits: sx1509q

	  Say yes here to provide support for Semtech SX150x-series I2C

	  GPIO expanders. The GPIO driver was replaced by a Pinctrl version.

config GPIO_TPIC2810

	tristate "TPIC2810 8-Bit I2C GPO expander"

config GPIO_TS4900

	tristate "Technologic Systems FPGA I2C GPIO"

	depends on SOC_IMX6 || COMPILE_TEST

	select REGMAP_I2C

	help

	  Say yes here to enabled the GPIO driver for Technologic's FPGA core.

	  This option enables support for on-chip GPIO found

	  on Analog Devices ADP5520 PMICs.

config GPIO_ALTERA_A10SR

	tristate "Altera Arria10 System Resource GPIO"

	depends on MFD_ALTERA_A10SR

	help

	  Driver for Arria10 Development Kit GPIO expansion which

	  includes reads of pushbuttons and DIP switches as well

	  as writes to LEDs.

config GPIO_ARIZONA

	tristate "Wolfson Microelectronics Arizona class devices"

	depends on MFD_ARIZONA

config GPIO_CRYSTAL_COVE

	tristate "GPIO support for Crystal Cove PMIC"

	depends on INTEL_SOC_PMIC

	depends on (X86 || COMPILE_TEST) && INTEL_SOC_PMIC

	select GPIOLIB_IRQCHIP

	help

	  Support for GPIO pins on Crystal Cove PMIC.

config GPIO_CS5535

	tristate "AMD CS5535/CS5536 GPIO support"

	depends on X86 || MIPS || COMPILE_TEST

	depends on MFD_CS5535

	help

	  The AMD CS5535 and CS5536 southbridges support 28 GPIO pins that

config GPIO_MSIC

	bool "Intel MSIC mixed signal gpio support"

	depends on MFD_INTEL_MSIC

	depends on (X86 || COMPILE_TEST) && MFD_INTEL_MSIC

	help

	  Enable support for GPIO on intel MSIC controllers found in

	  intel MID devices

config GPIO_WHISKEY_COVE

	tristate "GPIO support for Whiskey Cove PMIC"

	depends on INTEL_SOC_PMIC

	depends on (X86 || COMPILE_TEST) && INTEL_SOC_PMIC

	select GPIOLIB_IRQCHIP

	help

	  Support for GPIO pins on Whiskey Cove PMIC.

config GPIO_AMD8111

	tristate "AMD 8111 GPIO driver"

	depends on X86 || COMPILE_TEST

	help

	  The AMD 8111 south bridge contains 32 GPIO pins which can be used.

config GPIO_ML_IOH

	tristate "OKI SEMICONDUCTOR ML7213 IOH GPIO support"

	depends on X86 || COMPILE_TEST

	select GENERIC_IRQ_CHIP

	help

	  ML7213 is companion chip for Intel Atom E6xx series.