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Commit 0611858d authored by Ionela Voinescu's avatar Ionela Voinescu Committed by Todd Kjos
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UPSTREAM: arm64: trap to EL1 accesses to AMU counters from EL0 



The activity monitors extension is an optional extension introduced
by the ARMv8.4 CPU architecture. In order to access the activity
monitors counters safely, if desired, the kernel should detect the
presence of the extension through the feature register, and mediate
the access.

Therefore, disable direct accesses to activity monitors counters
from EL0 (userspace) and trap them to EL1 (kernel).

To be noted that the ARM64_AMU_EXTN kernel config does not have an
effect on this code. Given that the amuserenr_el0 resets to an
UNKNOWN value, setting the trap of EL0 accesses to EL1 is always
attempted for safety and security considerations. Therefore firmware
should still ensure accesses to AMU registers are not trapped in
EL2/EL3 as this code cannot be bypassed if the CPU implements the
Activity Monitors Unit.

Bug: 172781912
Change-Id: I231595cd2d1e36bfc6abd24559c9c3d13e7eab03
Signed-off-by: default avatarIonela Voinescu <ionela.voinescu@arm.com>
Reviewed-by: default avatarJames Morse <james.morse@arm.com>
Reviewed-by: default avatarValentin Schneider <valentin.schneider@arm.com>
Reviewed-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Cc: Steve Capper <steve.capper@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
(cherry picked from commit 87a1f063464afd934f0f22aac710ca65bef77af3)
Signed-off-by: default avatarNeeraj Upadhyay <neeraju@codeaurora.org>
parent 30bf0431

arch/arm64/include/asm/assembler.h

+10 −0
Original line number Diff line number Diff line
@@ -443,6 +443,16 @@ USER(\label, ic ivau, \tmp2) // invalidate I line PoU 
9000:

	.endm



/*

 * reset_amuserenr_el0 - reset AMUSERENR_EL0 if AMUv1 present

 */

	.macro	reset_amuserenr_el0, tmpreg

	mrs	\tmpreg, id_aa64pfr0_el1	// Check ID_AA64PFR0_EL1

	ubfx	\tmpreg, \tmpreg, #ID_AA64PFR0_AMU_SHIFT, #4

	cbz	\tmpreg, .Lskip_\@		// Skip if no AMU present

	msr_s	SYS_AMUSERENR_EL0, xzr		// Disable AMU access from EL0

.Lskip_\@:

	.endm

/*

 * copy_page - copy src to dest using temp registers t1-t8

 */

arch/arm64/mm/proc.S

+3 −0
Original line number Diff line number Diff line
@@ -138,6 +138,7 @@ alternative_endif 
	ubfx	x11, x11, #1, #1

	msr	oslar_el1, x11

	reset_pmuserenr_el0 x0			// Disable PMU access from EL0

	reset_amuserenr_el0 x0			// Disable AMU access from EL0



alternative_if ARM64_HAS_RAS_EXTN

	msr_s	SYS_DISR_EL1, xzr
@@ -430,6 +431,8 @@ ENTRY(__cpu_setup) 
	isb					// Unmask debug exceptions now,

	enable_dbg				// since this is per-cpu

	reset_pmuserenr_el0 x0			// Disable PMU access from EL0

	reset_amuserenr_el0 x0			// Disable AMU access from EL0



	/*

	 * Memory region attributes for LPAE:

	 *