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Commit 06019be3 authored by Akira Takeuchi's avatar Akira Takeuchi Committed by David Howells
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MN10300: Don't hard code the cacheline size in register defs 



Don't hard code the cacheline size in the cache control register definitions.

Signed-off-by: default avatarAkira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: default avatarKiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: default avatarDavid Howells <dhowells@redhat.com>
parent a1169564

arch/mn10300/include/asm/cache.h

+9 −5
Original line number Original line Diff line number Diff line
@@ -43,14 +43,18 @@ 




/* instruction cache access registers */

/* instruction cache access registers */

#define ICACHE_DATA(WAY, ENTRY, OFF) \

#define ICACHE_DATA(WAY, ENTRY, OFF) \

	__SYSREG(0xc8000000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10 + (OFF) * 4, u32)

	__SYSREG(0xc8000000 + (WAY) * L1_CACHE_WAYDISP + \

		(ENTRY) * L1_CACHE_BYTES + (OFF) * 4, u32)

#define ICACHE_TAG(WAY, ENTRY)	 \

#define ICACHE_TAG(WAY, ENTRY)	 \

	__SYSREG(0xc8100000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10, u32)

	__SYSREG(0xc8100000 + (WAY) * L1_CACHE_WAYDISP + \

		(ENTRY) * L1_CACHE_BYTES, u32)





/* instruction cache access registers */

/* data cache access registers */

#define DCACHE_DATA(WAY, ENTRY, OFF) \

#define DCACHE_DATA(WAY, ENTRY, OFF) \

	__SYSREG(0xc8200000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10 + (OFF) * 4, u32)

	__SYSREG(0xc8200000 + (WAY) * L1_CACHE_WAYDISP + \

		(ENTRY) * L1_CACHE_BYTES + (OFF) * 4, u32)

#define DCACHE_TAG(WAY, ENTRY)	 \

#define DCACHE_TAG(WAY, ENTRY)	 \

	__SYSREG(0xc8300000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10, u32)

	__SYSREG(0xc8300000 + (WAY) * L1_CACHE_WAYDISP + \

		(ENTRY) * L1_CACHE_BYTES, u32)





#endif /* _ASM_CACHE_H */
 
#endif /* _ASM_CACHE_H */