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Commit 05e062f9 authored by Fabio Estevam's avatar Fabio Estevam Committed by Shawn Guo
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clk: imx: clk-imx6q: Provide initial IPU clock settings for mx6dl 



Currently it is not possible to use HDMI and LVDS at the same time on a
imx6dl-sabresd board.

Fix this usecase by setting IMX6QDL_CLK_PLL3_PFD1_540M to 540MHz and
also by setting it as the parent of IMX6QDL_CLK_IPU1_SEL.

Based on the configuration done in the FSL kernel.

Signed-off-by: default avatarFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent d770e558

drivers/clk/imx/clk-imx6q.c

+4 −0
Original line number Diff line number Diff line
@@ -494,6 +494,10 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) 
		clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);

	}



	clk_set_rate(clk[IMX6QDL_CLK_PLL3_PFD1_540M], 540000000);

	if (clk_on_imx6dl())

		clk_set_parent(clk[IMX6QDL_CLK_IPU1_SEL], clk[IMX6QDL_CLK_PLL3_PFD1_540M]);



	clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);

	clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);

	clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);