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Commit 05ca1b32 authored by Russell King's avatar Russell King Committed by David S. Miller
Browse files

net: phy: marvell10g: update header comments 



Update header comments to indicate the newly found behaviour with XAUI
interfaces.

Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 3abbcccc

drivers/net/phy/marvell10g.c

+7 −1
Original line number Diff line number Diff line
@@ -6,12 +6,18 @@ 
 *

 * There appears to be several different data paths through the PHY which

 * are automatically managed by the PHY.  The following has been determined

 * via observation and experimentation:

 * via observation and experimentation for a setup using single-lane Serdes:

 *

 *       SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)

 *  10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)

 *  10GBASE-KR PHYXS -- BASE-R PCS -- Fiber

 *

 * With XAUI, observation shows:

 *

 *        XAUI PHYXS -- <appropriate PCS as above>

 *

 * and no switching of the host interface mode occurs.

 *

 * If both the fiber and copper ports are connected, the first to gain

 * link takes priority and the other port is completely locked out.

 */