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Commit 05aa1651 authored by bob picco's avatar bob picco Committed by David S. Miller
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sparc64: T5 PMU 



The T5 (niagara5) has different PCR related HV fast trap values and a new
HV API Group. This patch utilizes these and shares when possible with niagara4.

We use the same sparc_pmu niagara4_pmu. Should there be new effort to
obtain the MCU perf statistics then this would have to be changed.

Cc: sparclinux@vger.kernel.org
Signed-off-by: default avatarBob Picco <bob.picco@oracle.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 7c21d533

arch/sparc/include/asm/hypervisor.h

+11 −0
Original line number Original line Diff line number Diff line
@@ -2947,6 +2947,16 @@ unsigned long sun4v_vt_set_perfreg(unsigned long reg_num, 
				   unsigned long reg_val);

				   unsigned long reg_val);

#endif

#endif





#define	HV_FAST_T5_GET_PERFREG		0x1a8

#define	HV_FAST_T5_SET_PERFREG		0x1a9



#ifndef	__ASSEMBLY__

unsigned long sun4v_t5_get_perfreg(unsigned long reg_num,

				   unsigned long *reg_val);

unsigned long sun4v_t5_set_perfreg(unsigned long reg_num,

				   unsigned long reg_val);

#endif



/* Function numbers for HV_CORE_TRAP.  */

/* Function numbers for HV_CORE_TRAP.  */

#define HV_CORE_SET_VER			0x00

#define HV_CORE_SET_VER			0x00

#define HV_CORE_PUTCHAR			0x01

#define HV_CORE_PUTCHAR			0x01
@@ -2978,6 +2988,7 @@ unsigned long sun4v_vt_set_perfreg(unsigned long reg_num, 
#define HV_GRP_VF_CPU			0x0205

#define HV_GRP_VF_CPU			0x0205

#define HV_GRP_KT_CPU			0x0209

#define HV_GRP_KT_CPU			0x0209

#define HV_GRP_VT_CPU			0x020c

#define HV_GRP_VT_CPU			0x020c

#define HV_GRP_T5_CPU			0x0211

#define HV_GRP_DIAG			0x0300

#define HV_GRP_DIAG			0x0300





#ifndef __ASSEMBLY__

#ifndef __ASSEMBLY__

arch/sparc/kernel/hvapi.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -46,6 +46,7 @@ static struct api_info api_table[] = { 
	{ .group = HV_GRP_VF_CPU,				},

	{ .group = HV_GRP_VF_CPU,				},

	{ .group = HV_GRP_KT_CPU,				},

	{ .group = HV_GRP_KT_CPU,				},

	{ .group = HV_GRP_VT_CPU,				},

	{ .group = HV_GRP_VT_CPU,				},

	{ .group = HV_GRP_T5_CPU,				},

	{ .group = HV_GRP_DIAG,		.flags = FLAG_PRE_API	},

	{ .group = HV_GRP_DIAG,		.flags = FLAG_PRE_API	},

};

};

arch/sparc/kernel/hvcalls.S

+16 −0
Original line number Original line Diff line number Diff line
@@ -821,3 +821,19 @@ ENTRY(sun4v_vt_set_perfreg) 
	retl

	retl

	 nop

	 nop

ENDPROC(sun4v_vt_set_perfreg)

ENDPROC(sun4v_vt_set_perfreg)



ENTRY(sun4v_t5_get_perfreg)

	mov	%o1, %o4

	mov	HV_FAST_T5_GET_PERFREG, %o5

	ta	HV_FAST_TRAP

	stx	%o1, [%o4]

	retl

	 nop

ENDPROC(sun4v_t5_get_perfreg)



ENTRY(sun4v_t5_set_perfreg)

	mov	HV_FAST_T5_SET_PERFREG, %o5

	ta	HV_FAST_TRAP

	retl

	 nop

ENDPROC(sun4v_t5_set_perfreg)

arch/sparc/kernel/pcr.c

+43 −4
Original line number Original line Diff line number Diff line
@@ -191,12 +191,41 @@ static const struct pcr_ops n4_pcr_ops = { 
	.pcr_nmi_disable	= PCR_N4_PICNPT,

	.pcr_nmi_disable	= PCR_N4_PICNPT,

};

};





static u64 n5_pcr_read(unsigned long reg_num)

{

	unsigned long val;



	(void) sun4v_t5_get_perfreg(reg_num, &val);



	return val;

}



static void n5_pcr_write(unsigned long reg_num, u64 val)

{

	(void) sun4v_t5_set_perfreg(reg_num, val);

}



static const struct pcr_ops n5_pcr_ops = {

	.read_pcr		= n5_pcr_read,

	.write_pcr		= n5_pcr_write,

	.read_pic		= n4_pic_read,

	.write_pic		= n4_pic_write,

	.nmi_picl_value		= n4_picl_value,

	.pcr_nmi_enable		= (PCR_N4_PICNPT | PCR_N4_STRACE |

				   PCR_N4_UTRACE | PCR_N4_TOE |

				   (26 << PCR_N4_SL_SHIFT)),

	.pcr_nmi_disable	= PCR_N4_PICNPT,

};





static unsigned long perf_hsvc_group;

static unsigned long perf_hsvc_group;

static unsigned long perf_hsvc_major;

static unsigned long perf_hsvc_major;

static unsigned long perf_hsvc_minor;

static unsigned long perf_hsvc_minor;





static int __init register_perf_hsvc(void)

static int __init register_perf_hsvc(void)

{

{

	unsigned long hverror;



	if (tlb_type == hypervisor) {

	if (tlb_type == hypervisor) {

		switch (sun4v_chip_type) {

		switch (sun4v_chip_type) {

		case SUN4V_CHIP_NIAGARA1:

		case SUN4V_CHIP_NIAGARA1:
@@ -215,6 +244,10 @@ static int __init register_perf_hsvc(void) 
			perf_hsvc_group = HV_GRP_VT_CPU;

			perf_hsvc_group = HV_GRP_VT_CPU;

			break;

			break;





		case SUN4V_CHIP_NIAGARA5:

			perf_hsvc_group = HV_GRP_T5_CPU;

			break;



		default:

		default:

			return -ENODEV;

			return -ENODEV;

		}

		}
@@ -222,10 +255,12 @@ static int __init register_perf_hsvc(void) 




		perf_hsvc_major = 1;

		perf_hsvc_major = 1;

		perf_hsvc_minor = 0;

		perf_hsvc_minor = 0;

		if (sun4v_hvapi_register(perf_hsvc_group,

		hverror = sun4v_hvapi_register(perf_hsvc_group,

					       perf_hsvc_major,

					       perf_hsvc_major,

					 &perf_hsvc_minor)) {

					       &perf_hsvc_minor);

			printk("perfmon: Could not register hvapi.\n");

		if (hverror) {

			pr_err("perfmon: Could not register hvapi(0x%lx).\n",

			       hverror);

			return -ENODEV;

			return -ENODEV;

		}

		}

	}

	}
@@ -254,6 +289,10 @@ static int __init setup_sun4v_pcr_ops(void) 
		pcr_ops = &n4_pcr_ops;

		pcr_ops = &n4_pcr_ops;

		break;

		break;





	case SUN4V_CHIP_NIAGARA5:

		pcr_ops = &n5_pcr_ops;

		break;



	default:

	default:

		ret = -ENODEV;

		ret = -ENODEV;

		break;

		break;

arch/sparc/kernel/perf_event.c

+2 −1
Original line number Original line Diff line number Diff line
@@ -1662,7 +1662,8 @@ static bool __init supported_pmu(void) 
		sparc_pmu = &niagara2_pmu;

		sparc_pmu = &niagara2_pmu;

		return true;

		return true;

	}

	}

	if (!strcmp(sparc_pmu_type, "niagara4")) {

	if (!strcmp(sparc_pmu_type, "niagara4") ||

	    !strcmp(sparc_pmu_type, "niagara5")) {

		sparc_pmu = &niagara4_pmu;

		sparc_pmu = &niagara4_pmu;

		return true;

		return true;

	}

	}