Loading qcom/lahaina-smp2p.dtsi +13 −0 Original line number Diff line number Diff line Loading @@ -23,6 +23,19 @@ interrupt-controller; #interrupt-cells = <2>; }; smp2p_ipa_1_out: qcom,smp2p-ipa-1-out { qcom,entry-name = "ipa"; #qcom,smem-state-cells = <1>; }; /* ipa - inbound entry from mss */ smp2p_ipa_1_in: qcom,smp2p-ipa-1-in { qcom,entry-name = "ipa"; interrupt-controller; #interrupt-cells = <2>; }; }; qcom,smp2p-dsps { Loading qcom/lahaina.dtsi +13 −0 Original line number Diff line number Diff line Loading @@ -1780,6 +1780,19 @@ qcom,ram-collection-on-crash; qcom,secure-debug-check-action = <0>; /* smp2p information */ qcom,smp2p_map_ipa_1_out { compatible = "qcom,smp2p-map-ipa-1-out"; qcom,smem-states = <&smp2p_ipa_1_out 0>; qcom,smem-state-names = "ipa-smp2p-out"; }; qcom,smp2p_map_ipa_1_in { compatible = "qcom,smp2p-map-ipa-1-in"; interrupts-extended = <&smp2p_ipa_1_in 0 0>; interrupt-names = "ipa-smp2p-in"; }; ipa_smmu_ap: ipa_smmu_ap { compatible = "qcom,ipa-smmu-ap-cb"; iommus = <&apps_smmu 0x5C0 0x0>; Loading Loading
qcom/lahaina-smp2p.dtsi +13 −0 Original line number Diff line number Diff line Loading @@ -23,6 +23,19 @@ interrupt-controller; #interrupt-cells = <2>; }; smp2p_ipa_1_out: qcom,smp2p-ipa-1-out { qcom,entry-name = "ipa"; #qcom,smem-state-cells = <1>; }; /* ipa - inbound entry from mss */ smp2p_ipa_1_in: qcom,smp2p-ipa-1-in { qcom,entry-name = "ipa"; interrupt-controller; #interrupt-cells = <2>; }; }; qcom,smp2p-dsps { Loading
qcom/lahaina.dtsi +13 −0 Original line number Diff line number Diff line Loading @@ -1780,6 +1780,19 @@ qcom,ram-collection-on-crash; qcom,secure-debug-check-action = <0>; /* smp2p information */ qcom,smp2p_map_ipa_1_out { compatible = "qcom,smp2p-map-ipa-1-out"; qcom,smem-states = <&smp2p_ipa_1_out 0>; qcom,smem-state-names = "ipa-smp2p-out"; }; qcom,smp2p_map_ipa_1_in { compatible = "qcom,smp2p-map-ipa-1-in"; interrupts-extended = <&smp2p_ipa_1_in 0 0>; interrupt-names = "ipa-smp2p-in"; }; ipa_smmu_ap: ipa_smmu_ap { compatible = "qcom,ipa-smmu-ap-cb"; iommus = <&apps_smmu 0x5C0 0x0>; Loading