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Commit 0570bc8b authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'riscv/for-v5.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux 

Pull RISC-V updates from Paul Walmsley:

 - Hugepage support

 - "Image" header support for RISC-V kernel binaries, compatible with
   the current ARM64 "Image" header

 - Initial page table setup now split into two stages

 - CONFIG_SOC support (starting with SiFive SoCs)

 - Avoid reserving memory between RAM start and the kernel in
   setup_bootmem()

 - Enable high-res timers and dynamic tick in the RV64 defconfig

 - Remove long-deprecated gate area stubs

 - MAINTAINERS updates to switch to the newly-created shared RISC-V git
   tree, and to fix a get_maintainers.pl issue for patches involving
   SiFive E-mail addresses

Also, one integration fix to resolve a build problem introduced during
in the v5.3-rc1 merge window:

 - Fix build break after macro-to-function conversion in
   asm-generic/cacheflush.h

* tag 'riscv/for-v5.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  riscv: fix build break after macro-to-function conversion in generic cacheflush.h
  RISC-V: Add an Image header that boot loader can parse.
  RISC-V: Setup initial page tables in two stages
  riscv: remove free_initrd_mem
  riscv: ccache: Remove unused variable
  riscv: Introduce huge page support for 32/64bit kernel
  x86, arm64: Move ARCH_WANT_HUGE_PMD_SHARE config in arch/Kconfig
  RISC-V: Fix memory reservation in setup_bootmem()
  riscv: defconfig: enable SOC_SIFIVE
  riscv: select SiFive platform drivers with SOC_SIFIVE
  arch: riscv: add config option for building SiFive's SoC resource
  riscv: Remove gate area stubs
  MAINTAINERS: change the arch/riscv git tree to the new shared tree
  MAINTAINERS: don't automatically patches involving SiFive to the linux-riscv list
  RISC-V: defconfig: Enable NO_HZ_IDLE and HIGH_RES_TIMERS
parents 0e2a5b5b 2d69fbf3

Documentation/riscv/boot-image-header.txt

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+50 −0
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				Boot image header in RISC-V Linux

			=============================================



Author: Atish Patra <atish.patra@wdc.com>

Date  : 20 May 2019



This document only describes the boot image header details for RISC-V Linux.

The complete booting guide will be available at Documentation/riscv/booting.txt.



The following 64-byte header is present in decompressed Linux kernel image.



	u32 code0;		  /* Executable code */

	u32 code1; 		  /* Executable code */

	u64 text_offset;	  /* Image load offset, little endian */

	u64 image_size;		  /* Effective Image size, little endian */

	u64 flags;		  /* kernel flags, little endian */

	u32 version;		  /* Version of this header */

	u32 res1  = 0;		  /* Reserved */

	u64 res2  = 0;    	  /* Reserved */

	u64 magic = 0x5643534952; /* Magic number, little endian, "RISCV" */

	u32 res3;		  /* Reserved for additional RISC-V specific header */

	u32 res4;		  /* Reserved for PE COFF offset */



This header format is compliant with PE/COFF header and largely inspired from

ARM64 header. Thus, both ARM64 & RISC-V header can be combined into one common

header in future.



Notes:

- This header can also be reused to support EFI stub for RISC-V in future. EFI

  specification needs PE/COFF image header in the beginning of the kernel image

  in order to load it as an EFI application. In order to support EFI stub,

  code0 should be replaced with "MZ" magic string and res5(at offset 0x3c) should

  point to the rest of the PE/COFF header.



- version field indicate header version number.

	Bits 0:15  - Minor version

	Bits 16:31 - Major version



  This preserves compatibility across newer and older version of the header.

  The current version is defined as 0.1.



- res3 is reserved for offset to any other additional fields. This makes the

  header extendible in future. One example would be to accommodate ISA

  extension for RISC-V in future. For current version, it is set to be zero.



- In current header, the flag field has only one field.

	Bit 0: Kernel endianness. 1 if BE, 0 if LE.



- Image size is mandatory for boot loader to load kernel image. Booting will

  fail otherwise.

MAINTAINERS

+2 −2
Original line number Diff line number Diff line
@@ -13720,7 +13720,7 @@ RISC-V ARCHITECTURE 
M:	Palmer Dabbelt <palmer@sifive.com>

M:	Albert Ou <aou@eecs.berkeley.edu>

L:	linux-riscv@lists.infradead.org

T:	git git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux.git

T:	git git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git

S:	Supported

F:	arch/riscv/

K:	riscv
@@ -14582,7 +14582,7 @@ M: Paul Walmsley <paul.walmsley@sifive.com> 
L:	linux-riscv@lists.infradead.org

T:	git git://github.com/sifive/riscv-linux.git

S:	Supported

K:	sifive

K:	[^@]sifive

N:	sifive



SIFIVE FU540 SYSTEM-ON-CHIP

arch/Kconfig

+3 −0
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@@ -569,6 +569,9 @@ config HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD 
config HAVE_ARCH_HUGE_VMAP

	bool



config ARCH_WANT_HUGE_PMD_SHARE

	bool



config HAVE_ARCH_SOFT_DIRTY

	bool

arch/arm64/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -73,6 +73,7 @@ config ARM64 
	select ARCH_SUPPORTS_NUMA_BALANCING

	select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT

	select ARCH_WANT_FRAME_POINTERS

	select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)

	select ARCH_HAS_UBSAN_SANITIZE_ALL

	select ARM_AMBA

	select ARM_ARCH_TIMER
@@ -906,7 +907,6 @@ config SYS_SUPPORTS_HUGETLBFS 
	def_bool y



config ARCH_WANT_HUGE_PMD_SHARE

	def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)



config ARCH_HAS_CACHE_LINE_SIZE

	def_bool y

arch/riscv/Kconfig

+10 −0
Original line number Diff line number Diff line
@@ -52,6 +52,8 @@ config RISCV 
	select ARCH_HAS_MMIOWB

	select HAVE_EBPF_JIT if 64BIT

	select EDAC_SUPPORT

	select ARCH_HAS_GIGANTIC_PAGE

	select ARCH_WANT_HUGE_PMD_SHARE if 64BIT



config MMU

	def_bool y
@@ -66,6 +68,12 @@ config PAGE_OFFSET 
	default 0xffffffff80000000 if 64BIT && MAXPHYSMEM_2GB

	default 0xffffffe000000000 if 64BIT && MAXPHYSMEM_128GB



config ARCH_WANT_GENERAL_HUGETLB

	def_bool y



config SYS_SUPPORTS_HUGETLBFS

	def_bool y



config STACKTRACE_SUPPORT

	def_bool y
@@ -97,6 +105,8 @@ config PGTABLE_LEVELS 
	default 3 if 64BIT

	default 2



source "arch/riscv/Kconfig.socs"



menu "Platform type"



choice