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Commit 056b2053 authored by Soren Brinkmann's avatar Soren Brinkmann Committed by Mike Turquette
Browse files

clk: divider: Introduce CLK_DIVIDER_ALLOW_ZERO flag 



Dividers which have CLK_DIVIDER_ONE_BASED set have a redundant state,
being a divider value of zero. Some hardware implementations allow a
zero divider which simply doesn't alter the frequency. I.e. it acts like
a divide by one or bypassing the divider.
This flag is used to handle such HW in the clk-divider model.

Signed-off-by: default avatarSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent f640c0fa

drivers/clk/clk-divider.c

+3 −2
Original line number Original line Diff line number Diff line
@@ -109,7 +109,8 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw, 




	div = _get_div(divider, val);

	div = _get_div(divider, val);

	if (!div) {

	if (!div) {

		WARN(1, "%s: Invalid divisor for clock %s\n", __func__,

		WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),

			"%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",

			__clk_get_name(hw->clk));

			__clk_get_name(hw->clk));

		return parent_rate;

		return parent_rate;

	}

	}

include/linux/clk-provider.h

+7 −1
Original line number Original line Diff line number Diff line
@@ -249,9 +249,14 @@ struct clk_div_table { 
 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the

 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the

 * 	register plus one.  If CLK_DIVIDER_ONE_BASED is set then the divider is

 * 	register plus one.  If CLK_DIVIDER_ONE_BASED is set then the divider is

 * 	the raw value read from the register, with the value of zero considered

 * 	the raw value read from the register, with the value of zero considered

 * 	invalid

 *	invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.

 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from

 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from

 * 	the hardware register

 * 	the hardware register

 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors.  For dividers which have

 *	CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.

 *	Some hardware implementations gracefully handle this case and allow a

 *	zero divisor by not modifying their input clock

 *	(divide by one / bypass).

 */

 */

struct clk_divider {

struct clk_divider {

	struct clk_hw	hw;

	struct clk_hw	hw;
@@ -265,6 +270,7 @@ struct clk_divider { 




#define CLK_DIVIDER_ONE_BASED		BIT(0)

#define CLK_DIVIDER_ONE_BASED		BIT(0)

#define CLK_DIVIDER_POWER_OF_TWO	BIT(1)

#define CLK_DIVIDER_POWER_OF_TWO	BIT(1)

#define CLK_DIVIDER_ALLOW_ZERO		BIT(2)





extern const struct clk_ops clk_divider_ops;

extern const struct clk_ops clk_divider_ops;

struct clk *clk_register_divider(struct device *dev, const char *name,

struct clk *clk_register_divider(struct device *dev, const char *name,