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Commit 054d282d authored by Tom St Denis's avatar Tom St Denis Committed by Alex Deucher
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drm/amd/amdgpu: Add ENGINE_CNTL register to vcn10 headers 



Signed-off-by: default avatarTom St Denis <tom.stdenis@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8ce1f7e7

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h

+2 −0
Original line number Diff line number Diff line
@@ -141,6 +141,8 @@ 
#define mmUVD_GPCOM_VCPU_DATA0_BASE_IDX                                                                1

#define mmUVD_GPCOM_VCPU_DATA1                                                                         0x03c5

#define mmUVD_GPCOM_VCPU_DATA1_BASE_IDX                                                                1

#define mmUVD_ENGINE_CNTL                                                                              0x03c6

#define mmUVD_ENGINE_CNTL_BASE_IDX                                                                     1

#define mmUVD_UDEC_DBW_UV_ADDR_CONFIG                                                                  0x03d2

#define mmUVD_UDEC_DBW_UV_ADDR_CONFIG_BASE_IDX                                                         1

#define mmUVD_UDEC_ADDR_CONFIG                                                                         0x03d3

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

+5 −0
Original line number Diff line number Diff line
@@ -312,6 +312,11 @@ 
//UVD_GPCOM_VCPU_DATA1

#define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT                                                                    0x0

#define UVD_GPCOM_VCPU_DATA1__DATA1_MASK                                                                      0xFFFFFFFFL

//UVD_ENGINE_CNTL

#define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x1

#define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0

#define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x2

#define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1

//UVD_UDEC_DBW_UV_ADDR_CONFIG

#define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_PIPES__SHIFT                                                         0x0

#define UVD_UDEC_DBW_UV_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                              0x3