Merge "pinctrl: Add api to enable/disable wakeup capability for a gpio" (053a2be9) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/pinctrl/qcom/pinctrl-msm.c

+72 −1

Original line number	Diff line number	Diff line
		@@ -22,6 +22,7 @@
		#include <linux/reboot.h>
		#include <linux/pm.h>
		#include <linux/log2.h>
		#include <linux/bitmap.h>

		#include "../core.h"
		#include "../pinconf.h"
		@@ -31,6 +32,7 @@
		#define MAX_NR_GPIO 300
		#define MAX_NR_TILES 4
		#define PS_HOLD_OFFSET 0x820
		#define QUP_MASK GENMASK(5, 0)

		/**
		* struct msm_pinctrl - state for a pinctrl-msm device
		@@ -66,6 +68,8 @@ struct msm_pinctrl {
		void __iomem *regs[MAX_NR_TILES];
		};

		static struct msm_pinctrl *msm_pinctrl_data;

		#define MSM_ACCESSOR(name) \
		static u32 msm_readl_##name(struct msm_pinctrl *pctrl, \
		const struct msm_pingroup *g) \
		@@ -1128,6 +1132,72 @@ SIMPLE_DEV_PM_OPS(msm_pinctrl_dev_pm_ops, msm_pinctrl_suspend,

		EXPORT_SYMBOL(msm_pinctrl_dev_pm_ops);

		int msm_qup_write(u32 mode, u32 val)
		{
		int i;
		struct pinctrl_qup *regs = msm_pinctrl_data->soc->qup_regs;
		int num_regs = msm_pinctrl_data->soc->nqup_regs;

		/Iterate over modes/
		for (i = 0; i < num_regs; i++) {
		if (regs[i].mode == mode) {
		writel_relaxed(val & QUP_MASK,
		msm_pinctrl_data->regs[0] + regs[i].offset);
		return 0;
		}
		}

		return -ENOENT;
		}

		int msm_qup_read(unsigned int mode)
		{
		int i, val;
		struct pinctrl_qup *regs = msm_pinctrl_data->soc->qup_regs;
		int num_regs = msm_pinctrl_data->soc->nqup_regs;

		/Iterate over modes/
		for (i = 0; i < num_regs; i++) {
		if (regs[i].mode == mode) {
		val = readl_relaxed(msm_pinctrl_data->regs[0] +
		regs[i].offset);
		return val & QUP_MASK;
		}
		}

		return -ENOENT;
		}

		/*
		* msm_gpio_mpm_wake_set - API to make interrupt wakeup capable
		* @dev: Device corrsponding to pinctrl
		* @gpio: Gpio number to make interrupt wakeup capable
		* @enable: Enable/Disable wakeup capability
		*/
		int msm_gpio_mpm_wake_set(unsigned int gpio, bool enable)
		{
		const struct msm_pingroup *g;
		unsigned long flags;
		u32 val;

		g = &msm_pinctrl_data->soc->groups[gpio];
		if (g->wake_bit == -1)
		return -ENOENT;

		raw_spin_lock_irqsave(&msm_pinctrl_data->lock, flags);
		val = readl_relaxed(msm_pinctrl_data->regs[g->tile] + g->wake_reg);
		if (enable)
		val \|= BIT(g->wake_bit);
		else
		val &= ~BIT(g->wake_bit);

		writel_relaxed(val, msm_pinctrl_data->regs[g->tile] + g->wake_reg);
		raw_spin_unlock_irqrestore(&msm_pinctrl_data->lock, flags);

		return 0;
		}
		EXPORT_SYMBOL(msm_gpio_mpm_wake_set);

		int msm_pinctrl_probe(struct platform_device *pdev,
		const struct msm_pinctrl_soc_data *soc_data)
		{
		@@ -1136,7 +1206,8 @@ int msm_pinctrl_probe(struct platform_device *pdev,
		int ret;
		int i;

		pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
		msm_pinctrl_data = pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl),
		GFP_KERNEL);
		if (!pctrl)
		return -ENOMEM;

drivers/pinctrl/qcom/pinctrl-msm.h

+19 −0

Original line number	Diff line number	Diff line
		@@ -5,6 +5,8 @@
		#ifndef __PINCTRL_MSM_H__
		#define __PINCTRL_MSM_H__

		#include <linux/pinctrl/qcom-pinctrl.h>

		struct pinctrl_pin_desc;

		/**
		@@ -53,6 +55,8 @@ struct msm_function {
		* @intr_detection_width: Number of bits used for specifying interrupt type,
		* Should be 2 for SoCs that can detect both edges in hardware,
		* otherwise 1.
		* @wake_reg: Offset of the WAKEUP_INT_EN register from base tile
		* @wake_bit: Bit number for the corresponding gpio
		*/
		struct msm_pingroup {
		const char *name;
		@@ -91,6 +95,19 @@ struct msm_pingroup {
		unsigned intr_polarity_bit:5;
		unsigned intr_detection_bit:5;
		unsigned intr_detection_width:5;

		u32 wake_reg;
		unsigned int wake_bit;
		};

		/*
		* struct pinctrl_qup - Qup mode configuration
		* @mode: Qup i3c mode
		* @offset: Offset of the register
		*/
		struct pinctrl_qup {
		u32 mode;
		u32 offset;
		};

		/**
		@@ -116,6 +133,8 @@ struct msm_pinctrl_soc_data {
		const char const tiles;
		unsigned int ntiles;
		const int *reserved_gpios;
		struct pinctrl_qup *qup_regs;
		unsigned int nqup_regs;
		};

		extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops;

include/linux/pinctrl/qcom-pinctrl.h

0 → 100644

+16 −0

Original line number	Diff line number	Diff line
		/* SPDX-License-Identifier: GPL-2.0-only */
		/*
		* Copyright (c) 2019, The Linux Foundation. All rights reserved.
		*/

		#ifndef __LINUX_PINCTRL_MSM_H__
		#define __LINUX_PINCTRL_MSM_H__

		/* APIS to access qup_i3c registers */
		int msm_qup_write(u32 mode, u32 val);
		int msm_qup_read(u32 mode);

		/* API to write to mpm_wakeup registers */
		int msm_gpio_mpm_wake_set(unsigned int gpio, bool enable);

		#endif /* __LINUX_PINCTRL_MSM_H__ */