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Commit 0507ef8a authored by Sasha Neftin's avatar Sasha Neftin Committed by Jeff Kirsher
Browse files

igc: Add transmit and receive fastpath and interrupt handlers 



This patch adds support for allocating, configuring, and freeing Tx/Rx ring
resources.  With these changes in place the descriptor queues are in a
state where they are ready to transmit or receive if provided buffers.

This also adds the transmit and receive fastpath and interrupt handlers.
With this code in place the network device is now able to send and receive
frames over the network interface using a single queue.

Signed-off-by: default avatarSasha Neftin <sasha.neftin@intel.com>
Tested-by: default avatarAaron Brown <aaron.f.brown@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 13b5b7fd

drivers/net/ethernet/intel/igc/igc.h

+66 −0
Original line number Diff line number Diff line
@@ -32,13 +32,31 @@ extern char igc_driver_version[]; 
#define IGC_START_ITR			648 /* ~6000 ints/sec */

#define IGC_FLAG_HAS_MSI		BIT(0)

#define IGC_FLAG_QUEUE_PAIRS		BIT(4)

#define IGC_FLAG_NEED_LINK_UPDATE	BIT(9)

#define IGC_FLAG_HAS_MSIX		BIT(13)

#define IGC_FLAG_VLAN_PROMISC		BIT(15)



#define IGC_START_ITR			648 /* ~6000 ints/sec */

#define IGC_4K_ITR			980

#define IGC_20K_ITR			196

#define IGC_70K_ITR			56



#define IGC_DEFAULT_ITR		3 /* dynamic */

#define IGC_MAX_ITR_USECS	10000

#define IGC_MIN_ITR_USECS	10

#define NON_Q_VECTORS		1

#define MAX_MSIX_ENTRIES	10



/* TX/RX descriptor defines */

#define IGC_DEFAULT_TXD		256

#define IGC_DEFAULT_TX_WORK	128

#define IGC_MIN_TXD		80

#define IGC_MAX_TXD		4096



#define IGC_DEFAULT_RXD		256

#define IGC_MIN_RXD		80

#define IGC_MAX_RXD		4096



/* Transmit and receive queues */

#define IGC_MAX_RX_QUEUES		4

#define IGC_MAX_TX_QUEUES		4
@@ -85,6 +103,16 @@ extern char igc_driver_version[]; 
#define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN)

#endif



/* How many Rx Buffers do we bundle into one write to the hardware ? */

#define IGC_RX_BUFFER_WRITE	16 /* Must be power of 2 */



/* igc_test_staterr - tests bits within Rx descriptor status and error fields */

static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc,

				      const u32 stat_err_bits)

{

	return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);

}



enum igc_state_t {

	__IGC_TESTING,

	__IGC_RESETTING,
@@ -92,6 +120,27 @@ enum igc_state_t { 
	__IGC_PTP_TX_IN_PROGRESS,

};



enum igc_tx_flags {

	/* cmd_type flags */

	IGC_TX_FLAGS_VLAN	= 0x01,

	IGC_TX_FLAGS_TSO	= 0x02,

	IGC_TX_FLAGS_TSTAMP	= 0x04,



	/* olinfo flags */

	IGC_TX_FLAGS_IPV4	= 0x10,

	IGC_TX_FLAGS_CSUM	= 0x20,

};



/* The largest size we can write to the descriptor is 65535.  In order to

 * maintain a power of two alignment we have to limit ourselves to 32K.

 */

#define IGC_MAX_TXD_PWR		15

#define IGC_MAX_DATA_PER_TXD	BIT(IGC_MAX_TXD_PWR)



/* Tx Descriptors needed, worst case */

#define TXD_USE_COUNT(S)	DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD)

#define DESC_NEEDED	(MAX_SKB_FRAGS + 4)



/* wrapper around a pointer to a socket buffer,

 * so a DMA handle can be stored along with the buffer

 */
@@ -123,6 +172,7 @@ struct igc_tx_queue_stats { 
	u64 packets;

	u64 bytes;

	u64 restart_queue;

	u64 restart_queue2;

};



struct igc_rx_queue_stats {
@@ -181,11 +231,14 @@ struct igc_ring { 
		/* TX */

		struct {

			struct igc_tx_queue_stats tx_stats;

			struct u64_stats_sync tx_syncp;

			struct u64_stats_sync tx_syncp2;

		};

		/* RX */

		struct {

			struct igc_rx_queue_stats rx_stats;

			struct igc_rx_packet_stats pkt_stats;

			struct u64_stats_sync rx_syncp;

			struct sk_buff *skb;

		};

	};
@@ -258,11 +311,17 @@ struct igc_adapter { 
	struct work_struct watchdog_task;

	struct work_struct dma_err_task;



	u8 tx_timeout_factor;



	int msg_enable;

	u32 max_frame_size;

	u32 min_frame_size;



	/* OS defined structs */

	struct pci_dev *pdev;

	/* lock for statistics */

	spinlock_t stats64_lock;

	struct rtnl_link_stats64 stats64;



	/* structs defined in igc_hw.h */

	struct igc_hw hw;
@@ -275,8 +334,13 @@ struct igc_adapter { 
	u16 tx_ring_count;

	u16 rx_ring_count;



	u32 *shadow_vfta;



	u32 rss_queues;



	/* lock for RX network flow classification filter */

	spinlock_t nfc_lock;



	struct igc_mac_addr *mac_table;

};
@@ -332,6 +396,8 @@ static inline unsigned int igc_rx_pg_order(struct igc_ring *ring) 


#define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring))



#define IGC_TXD_DCMD	(IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS)



#define IGC_RX_DESC(R, i)       \

	(&(((union igc_adv_rx_desc *)((R)->desc))[i]))

#define IGC_TX_DESC(R, i)       \

drivers/net/ethernet/intel/igc/igc_base.h

+15 −0
Original line number Diff line number Diff line
@@ -21,6 +21,18 @@ union igc_adv_tx_desc { 
	} wb;

};



/* Adv Transmit Descriptor Config Masks */

#define IGC_ADVTXD_MAC_TSTAMP	0x00080000 /* IEEE1588 Timestamp packet */

#define IGC_ADVTXD_DTYP_CTXT	0x00200000 /* Advanced Context Descriptor */

#define IGC_ADVTXD_DTYP_DATA	0x00300000 /* Advanced Data Descriptor */

#define IGC_ADVTXD_DCMD_EOP	0x01000000 /* End of Packet */

#define IGC_ADVTXD_DCMD_IFCS	0x02000000 /* Insert FCS (Ethernet CRC) */

#define IGC_ADVTXD_DCMD_RS	0x08000000 /* Report Status */

#define IGC_ADVTXD_DCMD_DEXT	0x20000000 /* Descriptor extension (1=Adv) */

#define IGC_ADVTXD_DCMD_VLE	0x40000000 /* VLAN pkt enable */

#define IGC_ADVTXD_DCMD_TSE	0x80000000 /* TCP Seg enable */

#define IGC_ADVTXD_PAYLEN_SHIFT	14 /* Adv desc PAYLEN shift */



struct igc_adv_data_desc {

	__le64 buffer_addr;    /* Address of the descriptor's data buffer */

	union {
@@ -75,6 +87,9 @@ union igc_adv_rx_desc { 
	} wb;  /* writeback */

};



/* Adv Transmit Descriptor Config Masks */

#define IGC_ADVTXD_PAYLEN_SHIFT	14 /* Adv desc PAYLEN shift */



/* Additional Transmit Descriptor Control definitions */

#define IGC_TXDCTL_QUEUE_ENABLE	0x02000000 /* Ena specific Tx Queue */

drivers/net/ethernet/intel/igc/igc_defines.h

+45 −0
Original line number Diff line number Diff line
@@ -84,6 +84,29 @@ 
#define IGC_GPIE_EIAME		0x40000000

#define IGC_GPIE_PBA		0x80000000



/* Transmit Descriptor bit definitions */

#define IGC_TXD_DTYP_D		0x00100000 /* Data Descriptor */

#define IGC_TXD_DTYP_C		0x00000000 /* Context Descriptor */

#define IGC_TXD_POPTS_IXSM	0x01       /* Insert IP checksum */

#define IGC_TXD_POPTS_TXSM	0x02       /* Insert TCP/UDP checksum */

#define IGC_TXD_CMD_EOP		0x01000000 /* End of Packet */

#define IGC_TXD_CMD_IFCS	0x02000000 /* Insert FCS (Ethernet CRC) */

#define IGC_TXD_CMD_IC		0x04000000 /* Insert Checksum */

#define IGC_TXD_CMD_RS		0x08000000 /* Report Status */

#define IGC_TXD_CMD_RPS		0x10000000 /* Report Packet Sent */

#define IGC_TXD_CMD_DEXT	0x20000000 /* Desc extension (0 = legacy) */

#define IGC_TXD_CMD_VLE		0x40000000 /* Add VLAN tag */

#define IGC_TXD_CMD_IDE		0x80000000 /* Enable Tidv register */

#define IGC_TXD_STAT_DD		0x00000001 /* Descriptor Done */

#define IGC_TXD_STAT_EC		0x00000002 /* Excess Collisions */

#define IGC_TXD_STAT_LC		0x00000004 /* Late Collisions */

#define IGC_TXD_STAT_TU		0x00000008 /* Transmit underrun */

#define IGC_TXD_CMD_TCP		0x01000000 /* TCP packet */

#define IGC_TXD_CMD_IP		0x02000000 /* IP packet */

#define IGC_TXD_CMD_TSE		0x04000000 /* TCP Seg enable */

#define IGC_TXD_STAT_TC		0x00000004 /* Tx Underrun */

#define IGC_TXD_EXTCMD_TSTAMP	0x00000010 /* IEEE1588 Timestamp packet */



/* Transmit Control */

#define IGC_TCTL_EN		0x00000002 /* enable Tx */

#define IGC_TCTL_PSP		0x00000008 /* pad short packets */
@@ -111,6 +134,25 @@ 
#define IGC_RCTL_RDMTS_HALF	0x00000000 /* Rx desc min thresh size */

#define IGC_RCTL_BAM		0x00008000 /* broadcast enable */



/* Receive Descriptor bit definitions */

#define IGC_RXD_STAT_EOP	0x02    /* End of Packet */



#define IGC_RXDEXT_STATERR_CE		0x01000000

#define IGC_RXDEXT_STATERR_SE		0x02000000

#define IGC_RXDEXT_STATERR_SEQ		0x04000000

#define IGC_RXDEXT_STATERR_CXE		0x10000000

#define IGC_RXDEXT_STATERR_TCPE		0x20000000

#define IGC_RXDEXT_STATERR_IPE		0x40000000

#define IGC_RXDEXT_STATERR_RXE		0x80000000



/* Same mask, but for extended and packet split descriptors */

#define IGC_RXDEXT_ERR_FRAME_ERR_MASK ( \

	IGC_RXDEXT_STATERR_CE  |	\

	IGC_RXDEXT_STATERR_SE  |	\

	IGC_RXDEXT_STATERR_SEQ |	\

	IGC_RXDEXT_STATERR_CXE |	\

	IGC_RXDEXT_STATERR_RXE)



/* Header split receive */

#define IGC_RFCTL_IPV6_EX_DIS	0x00010000

#define IGC_RFCTL_LEF		0x00040000
@@ -123,6 +165,9 @@ 
#define IGC_RCTL_PMCF		0x00800000 /* pass MAC control frames */

#define IGC_RCTL_SECRC		0x04000000 /* Strip Ethernet CRC */



#define I225_RXPBSIZE_DEFAULT	0x000000A2 /* RXPBSIZE default */

#define I225_TXPBSIZE_DEFAULT	0x04000014 /* TXPBSIZE default */



#define IGC_N0_QUEUE -1



#endif /* _IGC_DEFINES_H_ */

drivers/net/ethernet/intel/igc/igc_main.c

+1079 −44

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