Loading bindings/gpu/adreno.txt +1 −0 Original line number Diff line number Diff line Loading @@ -8,6 +8,7 @@ Required properties: Must include "qcom,adreno-gpu-a619-holi" for Holi target. Must include "qcom,adreno-gpu-a642" for Shima target. Must include "qcom,adreno-gpu-a642l" for Yupik target. Must include "qcom,adreno-gpu-a643" for Yupik a643 target. - reg: Specifies the list of register regions for the device. - reg-names: Resource names used for the register regions specified in reg. Loading qcom/yupik-gpu.dtsi +22 −2 Original line number Diff line number Diff line Loading @@ -57,8 +57,8 @@ qcom,min-access-length = <32>; qcom,ubwc-mode = <3>; nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>; nvmem-cell-names = "speed_bin", "gaming_bin"; nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>, <&gpu_model_bin>; nvmem-cell-names = "speed_bin", "gaming_bin", "gpu_model"; qcom,tzone-names = "gpuss-0-usr", "gpuss-1-usr"; Loading Loading @@ -119,6 +119,26 @@ }; }; qcom,gpu-models { #address-cells = <1>; #size-cells = <0>; compatible="qcom,gpu-models"; qcom,gpu-model@0 { compatible="qcom,adreno-gpu-a643"; qcom,gpu-model-id = <172>; qcom,gpu-model = "Adreno643v1"; qcom,vk-device-id = <0x06030501>; }; qcom,gpu-model@1 { compatible="qcom,adreno-gpu-a643"; qcom,gpu-model-id = <190>; qcom,gpu-model = "Adreno643v1"; qcom,vk-device-id = <0x06030501>; }; }; qcom,gpu-mempools { #address-cells = <1>; #size-cells = <0>; Loading qcom/yupik.dtsi +5 −0 Original line number Diff line number Diff line Loading @@ -5047,6 +5047,11 @@ bits = <5 1>; }; gpu_model_bin: gpu_model_bin@1e9 { reg = <0x1e9 0x2>; bits = <5 8>; }; feat_conf_m7: feat_conf_m7@6020 { reg = <0x6020 0x4>; }; Loading Loading
bindings/gpu/adreno.txt +1 −0 Original line number Diff line number Diff line Loading @@ -8,6 +8,7 @@ Required properties: Must include "qcom,adreno-gpu-a619-holi" for Holi target. Must include "qcom,adreno-gpu-a642" for Shima target. Must include "qcom,adreno-gpu-a642l" for Yupik target. Must include "qcom,adreno-gpu-a643" for Yupik a643 target. - reg: Specifies the list of register regions for the device. - reg-names: Resource names used for the register regions specified in reg. Loading
qcom/yupik-gpu.dtsi +22 −2 Original line number Diff line number Diff line Loading @@ -57,8 +57,8 @@ qcom,min-access-length = <32>; qcom,ubwc-mode = <3>; nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>; nvmem-cell-names = "speed_bin", "gaming_bin"; nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>, <&gpu_model_bin>; nvmem-cell-names = "speed_bin", "gaming_bin", "gpu_model"; qcom,tzone-names = "gpuss-0-usr", "gpuss-1-usr"; Loading Loading @@ -119,6 +119,26 @@ }; }; qcom,gpu-models { #address-cells = <1>; #size-cells = <0>; compatible="qcom,gpu-models"; qcom,gpu-model@0 { compatible="qcom,adreno-gpu-a643"; qcom,gpu-model-id = <172>; qcom,gpu-model = "Adreno643v1"; qcom,vk-device-id = <0x06030501>; }; qcom,gpu-model@1 { compatible="qcom,adreno-gpu-a643"; qcom,gpu-model-id = <190>; qcom,gpu-model = "Adreno643v1"; qcom,vk-device-id = <0x06030501>; }; }; qcom,gpu-mempools { #address-cells = <1>; #size-cells = <0>; Loading
qcom/yupik.dtsi +5 −0 Original line number Diff line number Diff line Loading @@ -5047,6 +5047,11 @@ bits = <5 1>; }; gpu_model_bin: gpu_model_bin@1e9 { reg = <0x1e9 0x2>; bits = <5 8>; }; feat_conf_m7: feat_conf_m7@6020 { reg = <0x6020 0x4>; }; Loading