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Commit 04c532a1 authored by Ralf Goebel's avatar Ralf Goebel Committed by Joerg Roedel
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iommu/omap: Fix cache flushes on L2 table entries 



The base address used for DMA operations on the second-level table
did incorrectly include the offset for the table entry. The offset
was then added again which lead to incorrect behavior.

Operations on the L1 table are not affected.

The calculation of the base address is changed to point to the
beginning of the L2 table.

Fixes: bfee0cf0 ("iommu/omap: Use DMA-API for performing cache flushes")
Acked-by: default avatarSuman Anna <s-anna@ti.com>
Signed-off-by: default avatarRalf Goebel <ralf.goebel@imago-technologies.com>
Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
parent 1ffaddd0

drivers/iommu/omap-iommu.c

+2 −2
Original line number Diff line number Diff line
@@ -550,7 +550,7 @@ static u32 *iopte_alloc(struct omap_iommu *obj, u32 *iopgd, 


pte_ready:

	iopte = iopte_offset(iopgd, da);

	*pt_dma = virt_to_phys(iopte);

	*pt_dma = iopgd_page_paddr(iopgd);

	dev_vdbg(obj->dev,

		 "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n",

		 __func__, da, iopgd, *iopgd, iopte, *iopte);
@@ -738,7 +738,7 @@ static size_t iopgtable_clear_entry_core(struct omap_iommu *obj, u32 da) 
		}

		bytes *= nent;

		memset(iopte, 0, nent * sizeof(*iopte));

		pt_dma = virt_to_phys(iopte);

		pt_dma = iopgd_page_paddr(iopgd);

		flush_iopte_range(obj->dev, pt_dma, pt_offset, nent);



		/*