Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/next-queue (048856f4) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/net/ethernet/intel/ixgbe/ixgbe.h

+1 −0

Original line number	Original line	Diff line number	Diff line
	@@ -643,6 +643,7 @@ struct ixgbe_adapter {
	#define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP (u32)(1 << 8)		#define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP (u32)(1 << 8)
	#define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP (u32)(1 << 9)		#define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP (u32)(1 << 9)
	#define IXGBE_FLAG2_PTP_PPS_ENABLED (u32)(1 << 10)		#define IXGBE_FLAG2_PTP_PPS_ENABLED (u32)(1 << 10)
			#define IXGBE_FLAG2_PHY_INTERRUPT (u32)(1 << 11)

	/* Tx fast path data */		/* Tx fast path data */
	int num_tx_queues;		int num_tx_queues;

drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c

+2 −1

Original line number	Original line	Diff line number	Diff line
	@@ -1234,4 +1234,5 @@ struct ixgbe_info ixgbe_82598_info = {
	.mac_ops = &mac_ops_82598,		.mac_ops = &mac_ops_82598,
	.eeprom_ops = &eeprom_ops_82598,		.eeprom_ops = &eeprom_ops_82598,
	.phy_ops = &phy_ops_82598,		.phy_ops = &phy_ops_82598,
			.mvals = ixgbe_mvals_8259X,
	};		};

drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c

+4 −3

Original line number	Original line	Diff line number	Diff line
	@@ -71,7 +71,7 @@ bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
	{		{
	u32 fwsm, manc, factps;		u32 fwsm, manc, factps;

	fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);		fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
	if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)		if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
	return false;		return false;

	@@ -79,7 +79,7 @@ bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
	if (!(manc & IXGBE_MANC_RCV_TCO_EN))		if (!(manc & IXGBE_MANC_RCV_TCO_EN))
	return false;		return false;

	factps = IXGBE_READ_REG(hw, IXGBE_FACTPS);		factps = IXGBE_READ_REG(hw, IXGBE_FACTPS(hw));
	if (factps & IXGBE_FACTPS_MNGCG)		if (factps & IXGBE_FACTPS_MNGCG)
	return false;		return false;

	@@ -510,7 +510,7 @@ static void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw)
	hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2);		hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2);

	/* Check to see if MNG FW could be enabled */		/* Check to see if MNG FW could be enabled */
	fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);		fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));

	if (((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT) &&		if (((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT) &&
	!hw->wol_enabled &&		!hw->wol_enabled &&
	@@ -2378,4 +2378,5 @@ struct ixgbe_info ixgbe_82599_info = {
	.eeprom_ops = &eeprom_ops_82599,		.eeprom_ops = &eeprom_ops_82599,
	.phy_ops = &phy_ops_82599,		.phy_ops = &phy_ops_82599,
	.mbx_ops = &mbx_ops_generic,		.mbx_ops = &mbx_ops_generic,
			.mvals = ixgbe_mvals_8259X,
	};		};

drivers/net/ethernet/intel/ixgbe/ixgbe_common.c

+35 −28

Original line number	Original line	Diff line number	Diff line
	@@ -57,6 +57,11 @@ static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
	u16 offset);		u16 offset);
	static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw);		static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw);

			/* Base table for registers values that change by MAC */
			const u32 ixgbe_mvals_8259X[IXGBE_MVALS_IDX_LIMIT] = {
			IXGBE_MVALS_INIT(8259X)
			};

	/**		/**
	* ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow		* ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
	* control		* control
	@@ -91,6 +96,8 @@ bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
	case IXGBE_DEV_ID_82599_T3_LOM:		case IXGBE_DEV_ID_82599_T3_LOM:
	case IXGBE_DEV_ID_X540T:		case IXGBE_DEV_ID_X540T:
	case IXGBE_DEV_ID_X540T1:		case IXGBE_DEV_ID_X540T1:
			case IXGBE_DEV_ID_X550T:
			case IXGBE_DEV_ID_X550EM_X_10G_T:
	supported = true;		supported = true;
	break;		break;
	default:		default:
	@@ -463,7 +470,7 @@ s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
	}		}
	}		}

	if (hw->mac.type == ixgbe_mac_X540) {		if (hw->mac.type == ixgbe_mac_X550 \|\| hw->mac.type == ixgbe_mac_X540) {
	if (hw->phy.id == 0)		if (hw->phy.id == 0)
	hw->phy.ops.identify(hw);		hw->phy.ops.identify(hw);
	hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, MDIO_MMD_PCS, &i);		hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, MDIO_MMD_PCS, &i);
	@@ -681,7 +688,7 @@ void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
	bus->lan_id = bus->func;		bus->lan_id = bus->func;

	/* check for a port swap */		/* check for a port swap */
	reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);		reg = IXGBE_READ_REG(hw, IXGBE_FACTPS(hw));
	if (reg & IXGBE_FACTPS_LFS)		if (reg & IXGBE_FACTPS_LFS)
	bus->func ^= 0x1;		bus->func ^= 0x1;
	}		}
	@@ -799,7 +806,7 @@ s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
	* Check for EEPROM present first.		* Check for EEPROM present first.
	* If not present leave as none		* If not present leave as none
	*/		*/
	eec = IXGBE_READ_REG(hw, IXGBE_EEC);		eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
	if (eec & IXGBE_EEC_PRES) {		if (eec & IXGBE_EEC_PRES) {
	eeprom->type = ixgbe_eeprom_spi;		eeprom->type = ixgbe_eeprom_spi;

	@@ -1283,14 +1290,14 @@ static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
	if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)		if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
	return IXGBE_ERR_SWFW_SYNC;		return IXGBE_ERR_SWFW_SYNC;

	eec = IXGBE_READ_REG(hw, IXGBE_EEC);		eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));

	/* Request EEPROM Access */		/* Request EEPROM Access */
	eec \|= IXGBE_EEC_REQ;		eec \|= IXGBE_EEC_REQ;
	IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);		IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);

	for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {		for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
	eec = IXGBE_READ_REG(hw, IXGBE_EEC);		eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
	if (eec & IXGBE_EEC_GNT)		if (eec & IXGBE_EEC_GNT)
	break;		break;
	udelay(5);		udelay(5);
	@@ -1299,7 +1306,7 @@ static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
	/* Release if grant not acquired */		/* Release if grant not acquired */
	if (!(eec & IXGBE_EEC_GNT)) {		if (!(eec & IXGBE_EEC_GNT)) {
	eec &= ~IXGBE_EEC_REQ;		eec &= ~IXGBE_EEC_REQ;
	IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);		IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
	hw_dbg(hw, "Could not acquire EEPROM grant\n");		hw_dbg(hw, "Could not acquire EEPROM grant\n");

	hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);		hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
	@@ -1309,7 +1316,7 @@ static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
	/* Setup EEPROM for Read/Write */		/* Setup EEPROM for Read/Write */
	/* Clear CS and SK */		/* Clear CS and SK */
	eec &= ~(IXGBE_EEC_CS \| IXGBE_EEC_SK);		eec &= ~(IXGBE_EEC_CS \| IXGBE_EEC_SK);
	IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);		IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
	IXGBE_WRITE_FLUSH(hw);		IXGBE_WRITE_FLUSH(hw);
	udelay(1);		udelay(1);
	return 0;		return 0;
	@@ -1333,7 +1340,7 @@ static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
	* If the SMBI bit is 0 when we read it, then the bit will be		* If the SMBI bit is 0 when we read it, then the bit will be
	* set and we have the semaphore		* set and we have the semaphore
	*/		*/
	swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);		swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
	if (!(swsm & IXGBE_SWSM_SMBI))		if (!(swsm & IXGBE_SWSM_SMBI))
	break;		break;
	usleep_range(50, 100);		usleep_range(50, 100);
	@@ -1353,7 +1360,7 @@ static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
	* If the SMBI bit is 0 when we read it, then the bit will be		* If the SMBI bit is 0 when we read it, then the bit will be
	* set and we have the semaphore		* set and we have the semaphore
	*/		*/
	swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);		swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
	if (swsm & IXGBE_SWSM_SMBI) {		if (swsm & IXGBE_SWSM_SMBI) {
	hw_dbg(hw, "Software semaphore SMBI between device drivers not granted.\n");		hw_dbg(hw, "Software semaphore SMBI between device drivers not granted.\n");
	return IXGBE_ERR_EEPROM;		return IXGBE_ERR_EEPROM;
	@@ -1362,16 +1369,16 @@ static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)

	/* Now get the semaphore between SW/FW through the SWESMBI bit */		/* Now get the semaphore between SW/FW through the SWESMBI bit */
	for (i = 0; i < timeout; i++) {		for (i = 0; i < timeout; i++) {
	swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);		swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));

	/* Set the SW EEPROM semaphore bit to request access */		/* Set the SW EEPROM semaphore bit to request access */
	swsm \|= IXGBE_SWSM_SWESMBI;		swsm \|= IXGBE_SWSM_SWESMBI;
	IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);		IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm);

	/* If we set the bit successfully then we got the		/* If we set the bit successfully then we got the
	* semaphore.		* semaphore.
	*/		*/
	swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);		swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
	if (swsm & IXGBE_SWSM_SWESMBI)		if (swsm & IXGBE_SWSM_SWESMBI)
	break;		break;

	@@ -1400,11 +1407,11 @@ static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
	{		{
	u32 swsm;		u32 swsm;

	swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);		swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));

	/* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */		/* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
	swsm &= ~(IXGBE_SWSM_SWESMBI \| IXGBE_SWSM_SMBI);		swsm &= ~(IXGBE_SWSM_SWESMBI \| IXGBE_SWSM_SMBI);
	IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);		IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm);
	IXGBE_WRITE_FLUSH(hw);		IXGBE_WRITE_FLUSH(hw);
	}		}

	@@ -1454,15 +1461,15 @@ static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
	{		{
	u32 eec;		u32 eec;

	eec = IXGBE_READ_REG(hw, IXGBE_EEC);		eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));

	/* Toggle CS to flush commands */		/* Toggle CS to flush commands */
	eec \|= IXGBE_EEC_CS;		eec \|= IXGBE_EEC_CS;
	IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);		IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
	IXGBE_WRITE_FLUSH(hw);		IXGBE_WRITE_FLUSH(hw);
	udelay(1);		udelay(1);
	eec &= ~IXGBE_EEC_CS;		eec &= ~IXGBE_EEC_CS;
	IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);		IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
	IXGBE_WRITE_FLUSH(hw);		IXGBE_WRITE_FLUSH(hw);
	udelay(1);		udelay(1);
	}		}
	@@ -1480,7 +1487,7 @@ static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
	u32 mask;		u32 mask;
	u32 i;		u32 i;

	eec = IXGBE_READ_REG(hw, IXGBE_EEC);		eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));

	/*		/*
	* Mask is used to shift "count" bits of "data" out to the EEPROM		* Mask is used to shift "count" bits of "data" out to the EEPROM
	@@ -1501,7 +1508,7 @@ static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
	else		else
	eec &= ~IXGBE_EEC_DI;		eec &= ~IXGBE_EEC_DI;

	IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);		IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
	IXGBE_WRITE_FLUSH(hw);		IXGBE_WRITE_FLUSH(hw);

	udelay(1);		udelay(1);
	@@ -1518,7 +1525,7 @@ static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,

	/* We leave the "DI" bit set to "0" when we leave this routine. */		/* We leave the "DI" bit set to "0" when we leave this routine. */
	eec &= ~IXGBE_EEC_DI;		eec &= ~IXGBE_EEC_DI;
	IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);		IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
	IXGBE_WRITE_FLUSH(hw);		IXGBE_WRITE_FLUSH(hw);
	}		}

	@@ -1539,7 +1546,7 @@ static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
	* the value of the "DO" bit. During this "shifting in" process the		* the value of the "DO" bit. During this "shifting in" process the
	* "DI" bit should always be clear.		* "DI" bit should always be clear.
	*/		*/
	eec = IXGBE_READ_REG(hw, IXGBE_EEC);		eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));

	eec &= ~(IXGBE_EEC_DO \| IXGBE_EEC_DI);		eec &= ~(IXGBE_EEC_DO \| IXGBE_EEC_DI);

	@@ -1547,7 +1554,7 @@ static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
	data = data << 1;		data = data << 1;
	ixgbe_raise_eeprom_clk(hw, &eec);		ixgbe_raise_eeprom_clk(hw, &eec);

	eec = IXGBE_READ_REG(hw, IXGBE_EEC);		eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));

	eec &= ~(IXGBE_EEC_DI);		eec &= ~(IXGBE_EEC_DI);
	if (eec & IXGBE_EEC_DO)		if (eec & IXGBE_EEC_DO)
	@@ -1571,7 +1578,7 @@ static void ixgbe_raise_eeprom_clk(struct ixgbe_hw hw, u32 eec)
	* (setting the SK bit), then delay		* (setting the SK bit), then delay
	*/		*/
	eec = eec \| IXGBE_EEC_SK;		eec = eec \| IXGBE_EEC_SK;
	IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);		IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec);
	IXGBE_WRITE_FLUSH(hw);		IXGBE_WRITE_FLUSH(hw);
	udelay(1);		udelay(1);
	}		}
	@@ -1588,7 +1595,7 @@ static void ixgbe_lower_eeprom_clk(struct ixgbe_hw hw, u32 eec)
	* delay		* delay
	*/		*/
	eec = eec & ~IXGBE_EEC_SK;		eec = eec & ~IXGBE_EEC_SK;
	IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);		IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec);
	IXGBE_WRITE_FLUSH(hw);		IXGBE_WRITE_FLUSH(hw);
	udelay(1);		udelay(1);
	}		}
	@@ -1601,19 +1608,19 @@ static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
	{		{
	u32 eec;		u32 eec;

	eec = IXGBE_READ_REG(hw, IXGBE_EEC);		eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));

	eec \|= IXGBE_EEC_CS; /* Pull CS high */		eec \|= IXGBE_EEC_CS; /* Pull CS high */
	eec &= ~IXGBE_EEC_SK; /* Lower SCK */		eec &= ~IXGBE_EEC_SK; /* Lower SCK */

	IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);		IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
	IXGBE_WRITE_FLUSH(hw);		IXGBE_WRITE_FLUSH(hw);

	udelay(1);		udelay(1);

	/* Stop requesting EEPROM access */		/* Stop requesting EEPROM access */
	eec &= ~IXGBE_EEC_REQ;		eec &= ~IXGBE_EEC_REQ;
	IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);		IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);

	hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);		hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);

drivers/net/ethernet/intel/ixgbe/ixgbe_common.h

+2 −0

Original line number	Original line	Diff line number	Diff line
	@@ -118,6 +118,8 @@ bool ixgbe_mng_enabled(struct ixgbe_hw *hw);
	void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb,		void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb,
	u32 headroom, int strategy);		u32 headroom, int strategy);

			extern const u32 ixgbe_mvals_8259X[IXGBE_MVALS_IDX_LIMIT];

	#define IXGBE_I2C_THERMAL_SENSOR_ADDR 0xF8		#define IXGBE_I2C_THERMAL_SENSOR_ADDR 0xF8
	#define IXGBE_EMC_INTERNAL_DATA 0x00		#define IXGBE_EMC_INTERNAL_DATA 0x00
	#define IXGBE_EMC_INTERNAL_THERM_LIMIT 0x20		#define IXGBE_EMC_INTERNAL_THERM_LIMIT 0x20