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Commit 04577994 authored by Haojian Zhuang's avatar Haojian Zhuang Committed by Mike Turquette
Browse files

clk: gate: add CLK_GATE_HIWORD_MASK 



In Rockchip Cortex-A9 based chips, they don't use paradigm of
reading-changing-writing the register contents.  Instead they
use a hiword mask to indicate the changed bits.

When b1 should be set as gate, it also needs to indicate the change
by setting hiword mask (b1 << 16).

The patch adds gate flag for this usage.

Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
Signed-off-by: default avatarHaojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent d57dfe75

drivers/clk/clk-gate.c

+19 −6
Original line number Diff line number Diff line
@@ -53,12 +53,18 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable) 
	if (gate->lock)

		spin_lock_irqsave(gate->lock, flags);



	if (gate->flags & CLK_GATE_HIWORD_MASK) {

		reg = BIT(gate->bit_idx + 16);

		if (set)

			reg |= BIT(gate->bit_idx);

	} else {

		reg = readl(gate->reg);



		if (set)

			reg |= BIT(gate->bit_idx);

		else

			reg &= ~BIT(gate->bit_idx);

	}



	writel(reg, gate->reg);
@@ -121,6 +127,13 @@ struct clk *clk_register_gate(struct device *dev, const char *name, 
	struct clk *clk;

	struct clk_init_data init;



	if (clk_gate_flags & CLK_GATE_HIWORD_MASK) {

		if (bit_idx > 16) {

			pr_err("gate bit exceeds LOWORD field\n");

			return ERR_PTR(-EINVAL);

		}

	}



	/* allocate the gate */

	gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);

	if (!gate) {

include/linux/clk-provider.h

+5 −0
Original line number Diff line number Diff line
@@ -210,6 +210,10 @@ void of_fixed_clk_setup(struct device_node *np); 
 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to

 * 	enable the clock.  Setting this flag does the opposite: setting the bit

 * 	disable the clock and clearing it enables the clock

 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit

 *   of this register, and mask of gate bits are in higher 16-bit of this

 *   register.  While setting the gate bits, higher 16-bit should also be

 *   updated to indicate changing gate bits.

 */

struct clk_gate {

	struct clk_hw hw;
@@ -220,6 +224,7 @@ struct clk_gate { 
};



#define CLK_GATE_SET_TO_DISABLE		BIT(0)

#define CLK_GATE_HIWORD_MASK		BIT(1)



extern const struct clk_ops clk_gate_ops;

struct clk *clk_register_gate(struct device *dev, const char *name,