Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 0398b95f authored by Adam Buchbinder's avatar Adam Buchbinder Committed by Jiri Kosina
Browse files

c6x: Fix misspellings in comments.

parent e0b1c817
Loading
Loading
Loading
Loading
+1 −1
Original line number Original line Diff line number Diff line
@@ -101,7 +101,7 @@ struct clk {
#define CLK_PLL			BIT(2) /* PLL-derived clock */
#define CLK_PLL			BIT(2) /* PLL-derived clock */
#define PRE_PLL			BIT(3) /* source is before PLL mult/div */
#define PRE_PLL			BIT(3) /* source is before PLL mult/div */
#define FIXED_DIV_PLL		BIT(4) /* fixed divisor from PLL */
#define FIXED_DIV_PLL		BIT(4) /* fixed divisor from PLL */
#define FIXED_RATE_PLL		BIT(5) /* fixed ouput rate PLL */
#define FIXED_RATE_PLL		BIT(5) /* fixed output rate PLL */


#define MAX_PLL_SYSCLKS 16
#define MAX_PLL_SYSCLKS 16


+1 −1
Original line number Original line Diff line number Diff line
@@ -145,7 +145,7 @@ static void cache_block_operation(unsigned int *start,
		spin_lock_irqsave(&cache_lock, flags);
		spin_lock_irqsave(&cache_lock, flags);


		/*
		/*
		 * If another cache operation is occuring
		 * If another cache operation is occurring
		 */
		 */
		if (unlikely(imcr_get(wc_reg))) {
		if (unlikely(imcr_get(wc_reg))) {
			spin_unlock_irqrestore(&cache_lock, flags);
			spin_unlock_irqrestore(&cache_lock, flags);