Loading drivers/gpu/msm/a6xx_reg.h +2 −1 Original line number Diff line number Diff line /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef _A6XX_REG_H Loading Loading @@ -394,6 +394,7 @@ #define A6XX_RBBM_ISDB_CNT 0x533 #define A6XX_RBBM_NC_MODE_CNTL 0X534 #define A6XX_RBBM_SNAPSHOT_STATUS 0x535 #define A6XX_RBBM_SECVID_TRUST_CNTL 0xF400 #define A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO 0xF800 Loading drivers/gpu/msm/adreno_a6xx_snapshot.c +40 −8 Original line number Diff line number Diff line // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include "adreno.h" Loading Loading @@ -805,6 +805,22 @@ static void a6xx_snapshot_shader(struct kgsl_device *device, } } static void a650_snapshot_mempool(struct kgsl_device *device, struct kgsl_snapshot *snapshot) { u32 val; /* set CP_CHICKEN_DBG[StabilizeMVC] to stabilize it while dumping */ kgsl_regread(device, A6XX_CP_CHICKEN_DBG, &val); kgsl_regwrite(device, A6XX_CP_CHICKEN_DBG, val | BIT(2)); kgsl_snapshot_indexed_registers(device, snapshot, A6XX_CP_MEM_POOL_DBG_ADDR, A6XX_CP_MEM_POOL_DBG_DATA, 0, 0x2100); kgsl_regwrite(device, A6XX_CP_CHICKEN_DBG, val); } static void a6xx_snapshot_mempool(struct kgsl_device *device, struct kgsl_snapshot *snapshot) { Loading @@ -817,7 +833,7 @@ static void a6xx_snapshot_mempool(struct kgsl_device *device, kgsl_snapshot_indexed_registers(device, snapshot, A6XX_CP_MEM_POOL_DBG_ADDR, A6XX_CP_MEM_POOL_DBG_DATA, 0, 0x2060); 0, 0x2100); /* * Data at offset 0x2000 in the mempool section is the mempool size. Loading Loading @@ -1765,7 +1781,7 @@ void a6xx_snapshot(struct adreno_device *adreno_dev, struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev); struct adreno_ringbuffer *rb; bool sptprac_on; unsigned int i, roq_size, ucode_dbg_size; unsigned int i, roq_size; /* GMU TCM data dumped through AHB */ gmu_core_dev_snapshot(device, snapshot); Loading Loading @@ -1814,6 +1830,10 @@ void a6xx_snapshot(struct adreno_device *adreno_dev, if (!gmu_core_dev_gx_is_on(device)) return; /* Assert the isStatic bit before triggering snapshot */ if (adreno_is_a660(adreno_dev)) kgsl_regwrite(device, A6XX_RBBM_SNAPSHOT_STATUS, 0x1); /* Dump the registers which get affected by crash dumper trigger */ kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_REGS, snapshot, a6xx_snapshot_pre_crashdump_regs, NULL); Loading Loading @@ -1846,13 +1866,10 @@ void a6xx_snapshot(struct adreno_device *adreno_dev, A6XX_CP_DRAW_STATE_ADDR, A6XX_CP_DRAW_STATE_DATA, 0, 0x100); ucode_dbg_size = adreno_is_a650_family(adreno_dev) ? 0x7000 : 0x6000; /* SQE_UCODE Cache */ kgsl_snapshot_indexed_registers(device, snapshot, A6XX_CP_SQE_UCODE_DBG_ADDR, A6XX_CP_SQE_UCODE_DBG_DATA, 0, ucode_dbg_size); 0, 0x8000); /* * CP ROQ dump units is 4dwords. The number of units is stored Loading @@ -1869,6 +1886,9 @@ void a6xx_snapshot(struct adreno_device *adreno_dev, snapshot, a6xx_snapshot_sqe, NULL); /* Mempool debug data */ if (adreno_is_a650_family(adreno_dev)) a650_snapshot_mempool(device, snapshot); else a6xx_snapshot_mempool(device, snapshot); if (sptprac_on) { Loading @@ -1882,6 +1902,18 @@ void a6xx_snapshot(struct adreno_device *adreno_dev, a6xx_snapshot_dbgahb_regs(device, snapshot); } if (adreno_is_a660(adreno_dev)) { u32 val; kgsl_regread(device, A6XX_RBBM_SNAPSHOT_STATUS, &val); if (!val) dev_err(device->dev, "Interface signals may have changed during snapshot\n"); kgsl_regwrite(device, A6XX_RBBM_SNAPSHOT_STATUS, 0x0); } /* Preemption record */ if (adreno_is_preemption_enabled(adreno_dev)) { FOR_EACH_RINGBUFFER(adreno_dev, rb, i) { Loading drivers/gpu/msm/kgsl_bus.c +17 −4 Original line number Diff line number Diff line // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2019, The Linux Foundation. All rights reserved. * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #include <linux/interconnect.h> Loading Loading @@ -147,15 +147,28 @@ u32 *kgsl_bus_get_table(struct platform_device *pdev, int kgsl_bus_init(struct kgsl_device *device, struct platform_device *pdev) { struct kgsl_pwrctrl *pwr = &device->pwrctrl; int ret, count; int count; int ddr = of_fdt_get_ddrtype(); if (ddr >= 0) { char str[32]; snprintf(str, sizeof(str), "qcom,bus-table-ddr%d", ddr); pwr->ddr_table = kgsl_bus_get_table(pdev, str, &count); if (!IS_ERR(pwr->ddr_table)) goto done; } /* Look if a generic table is present */ pwr->ddr_table = kgsl_bus_get_table(pdev, "qcom,bus-table-ddr", &count); if (IS_ERR(pwr->ddr_table)) { ret = PTR_ERR(pwr->ddr_table); int ret = PTR_ERR(pwr->ddr_table); pwr->ddr_table = NULL; return ret; } done: pwr->ddr_table_count = count; validate_pwrlevels(device, pwr->ddr_table, pwr->ddr_table_count); Loading drivers/gpu/msm/kgsl_gmu.c +3 −6 Original line number Diff line number Diff line Loading @@ -1390,8 +1390,6 @@ static int gmu_probe(struct kgsl_device *device, struct device_node *node) gmu->num_gpupwrlevels = pwr->num_pwrlevels + 1; gmu->icc_path = of_icc_get(&gmu->pdev->dev, NULL); /* Populates RPMh configurations */ ret = gmu_rpmh_init(device, gmu); if (ret) Loading Loading @@ -1572,7 +1570,7 @@ static int gmu_start(struct kgsl_device *device) /* Vote for minimal DDR BW for GMU to init */ level = pwr->pwrlevels[pwr->default_pwrlevel].bus_min; icc_set_bw(gmu->icc_path, 0, icc_set_bw(pwr->icc_path, 0, MBps_to_icc(pwr->ddr_table[level])); ret = gmu_dev_ops->rpmh_gpu_pwrctrl(device, GMU_FW_START, Loading Loading @@ -1650,6 +1648,7 @@ static void gmu_stop(struct kgsl_device *device) { struct gmu_device *gmu = KGSL_GMU_DEVICE(device); struct gmu_dev_ops *gmu_dev_ops = GMU_DEVICE_OPS(device); struct kgsl_pwrctrl *pwr = &device->pwrctrl; int ret = 0; if (!test_bit(GMU_CLK_ON, &device->gmu_core.flags)) Loading @@ -1676,7 +1675,7 @@ static void gmu_stop(struct kgsl_device *device) gmu_disable_clks(device); gmu_disable_gdsc(gmu); icc_set_bw(gmu->icc_path, 0, 0); icc_set_bw(pwr->icc_path, 0, 0); return; error: Loading Loading @@ -1710,8 +1709,6 @@ static void gmu_remove(struct kgsl_device *device) clear_bit(ADRENO_ACD_CTRL, &adreno_dev->pwrctrl_flag); icc_put(gmu->icc_path); if (gmu->fw_image) { release_firmware(gmu->fw_image); gmu->fw_image = NULL; Loading drivers/gpu/msm/kgsl_gmu.h +1 −3 Original line number Diff line number Diff line /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef __KGSL_GMU_H #define __KGSL_GMU_H Loading Loading @@ -210,8 +210,6 @@ struct gmu_device { unsigned long kmem_bitmap; const struct gmu_vma_entry *vma; unsigned int log_wptr_retention; /** @icc_path: Interconnect path for the GMU */ struct icc_path *icc_path; }; struct gmu_memdesc *gmu_get_memdesc(struct gmu_device *gmu, Loading Loading
drivers/gpu/msm/a6xx_reg.h +2 −1 Original line number Diff line number Diff line /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef _A6XX_REG_H Loading Loading @@ -394,6 +394,7 @@ #define A6XX_RBBM_ISDB_CNT 0x533 #define A6XX_RBBM_NC_MODE_CNTL 0X534 #define A6XX_RBBM_SNAPSHOT_STATUS 0x535 #define A6XX_RBBM_SECVID_TRUST_CNTL 0xF400 #define A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO 0xF800 Loading
drivers/gpu/msm/adreno_a6xx_snapshot.c +40 −8 Original line number Diff line number Diff line // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include "adreno.h" Loading Loading @@ -805,6 +805,22 @@ static void a6xx_snapshot_shader(struct kgsl_device *device, } } static void a650_snapshot_mempool(struct kgsl_device *device, struct kgsl_snapshot *snapshot) { u32 val; /* set CP_CHICKEN_DBG[StabilizeMVC] to stabilize it while dumping */ kgsl_regread(device, A6XX_CP_CHICKEN_DBG, &val); kgsl_regwrite(device, A6XX_CP_CHICKEN_DBG, val | BIT(2)); kgsl_snapshot_indexed_registers(device, snapshot, A6XX_CP_MEM_POOL_DBG_ADDR, A6XX_CP_MEM_POOL_DBG_DATA, 0, 0x2100); kgsl_regwrite(device, A6XX_CP_CHICKEN_DBG, val); } static void a6xx_snapshot_mempool(struct kgsl_device *device, struct kgsl_snapshot *snapshot) { Loading @@ -817,7 +833,7 @@ static void a6xx_snapshot_mempool(struct kgsl_device *device, kgsl_snapshot_indexed_registers(device, snapshot, A6XX_CP_MEM_POOL_DBG_ADDR, A6XX_CP_MEM_POOL_DBG_DATA, 0, 0x2060); 0, 0x2100); /* * Data at offset 0x2000 in the mempool section is the mempool size. Loading Loading @@ -1765,7 +1781,7 @@ void a6xx_snapshot(struct adreno_device *adreno_dev, struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev); struct adreno_ringbuffer *rb; bool sptprac_on; unsigned int i, roq_size, ucode_dbg_size; unsigned int i, roq_size; /* GMU TCM data dumped through AHB */ gmu_core_dev_snapshot(device, snapshot); Loading Loading @@ -1814,6 +1830,10 @@ void a6xx_snapshot(struct adreno_device *adreno_dev, if (!gmu_core_dev_gx_is_on(device)) return; /* Assert the isStatic bit before triggering snapshot */ if (adreno_is_a660(adreno_dev)) kgsl_regwrite(device, A6XX_RBBM_SNAPSHOT_STATUS, 0x1); /* Dump the registers which get affected by crash dumper trigger */ kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_REGS, snapshot, a6xx_snapshot_pre_crashdump_regs, NULL); Loading Loading @@ -1846,13 +1866,10 @@ void a6xx_snapshot(struct adreno_device *adreno_dev, A6XX_CP_DRAW_STATE_ADDR, A6XX_CP_DRAW_STATE_DATA, 0, 0x100); ucode_dbg_size = adreno_is_a650_family(adreno_dev) ? 0x7000 : 0x6000; /* SQE_UCODE Cache */ kgsl_snapshot_indexed_registers(device, snapshot, A6XX_CP_SQE_UCODE_DBG_ADDR, A6XX_CP_SQE_UCODE_DBG_DATA, 0, ucode_dbg_size); 0, 0x8000); /* * CP ROQ dump units is 4dwords. The number of units is stored Loading @@ -1869,6 +1886,9 @@ void a6xx_snapshot(struct adreno_device *adreno_dev, snapshot, a6xx_snapshot_sqe, NULL); /* Mempool debug data */ if (adreno_is_a650_family(adreno_dev)) a650_snapshot_mempool(device, snapshot); else a6xx_snapshot_mempool(device, snapshot); if (sptprac_on) { Loading @@ -1882,6 +1902,18 @@ void a6xx_snapshot(struct adreno_device *adreno_dev, a6xx_snapshot_dbgahb_regs(device, snapshot); } if (adreno_is_a660(adreno_dev)) { u32 val; kgsl_regread(device, A6XX_RBBM_SNAPSHOT_STATUS, &val); if (!val) dev_err(device->dev, "Interface signals may have changed during snapshot\n"); kgsl_regwrite(device, A6XX_RBBM_SNAPSHOT_STATUS, 0x0); } /* Preemption record */ if (adreno_is_preemption_enabled(adreno_dev)) { FOR_EACH_RINGBUFFER(adreno_dev, rb, i) { Loading
drivers/gpu/msm/kgsl_bus.c +17 −4 Original line number Diff line number Diff line // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2019, The Linux Foundation. All rights reserved. * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #include <linux/interconnect.h> Loading Loading @@ -147,15 +147,28 @@ u32 *kgsl_bus_get_table(struct platform_device *pdev, int kgsl_bus_init(struct kgsl_device *device, struct platform_device *pdev) { struct kgsl_pwrctrl *pwr = &device->pwrctrl; int ret, count; int count; int ddr = of_fdt_get_ddrtype(); if (ddr >= 0) { char str[32]; snprintf(str, sizeof(str), "qcom,bus-table-ddr%d", ddr); pwr->ddr_table = kgsl_bus_get_table(pdev, str, &count); if (!IS_ERR(pwr->ddr_table)) goto done; } /* Look if a generic table is present */ pwr->ddr_table = kgsl_bus_get_table(pdev, "qcom,bus-table-ddr", &count); if (IS_ERR(pwr->ddr_table)) { ret = PTR_ERR(pwr->ddr_table); int ret = PTR_ERR(pwr->ddr_table); pwr->ddr_table = NULL; return ret; } done: pwr->ddr_table_count = count; validate_pwrlevels(device, pwr->ddr_table, pwr->ddr_table_count); Loading
drivers/gpu/msm/kgsl_gmu.c +3 −6 Original line number Diff line number Diff line Loading @@ -1390,8 +1390,6 @@ static int gmu_probe(struct kgsl_device *device, struct device_node *node) gmu->num_gpupwrlevels = pwr->num_pwrlevels + 1; gmu->icc_path = of_icc_get(&gmu->pdev->dev, NULL); /* Populates RPMh configurations */ ret = gmu_rpmh_init(device, gmu); if (ret) Loading Loading @@ -1572,7 +1570,7 @@ static int gmu_start(struct kgsl_device *device) /* Vote for minimal DDR BW for GMU to init */ level = pwr->pwrlevels[pwr->default_pwrlevel].bus_min; icc_set_bw(gmu->icc_path, 0, icc_set_bw(pwr->icc_path, 0, MBps_to_icc(pwr->ddr_table[level])); ret = gmu_dev_ops->rpmh_gpu_pwrctrl(device, GMU_FW_START, Loading Loading @@ -1650,6 +1648,7 @@ static void gmu_stop(struct kgsl_device *device) { struct gmu_device *gmu = KGSL_GMU_DEVICE(device); struct gmu_dev_ops *gmu_dev_ops = GMU_DEVICE_OPS(device); struct kgsl_pwrctrl *pwr = &device->pwrctrl; int ret = 0; if (!test_bit(GMU_CLK_ON, &device->gmu_core.flags)) Loading @@ -1676,7 +1675,7 @@ static void gmu_stop(struct kgsl_device *device) gmu_disable_clks(device); gmu_disable_gdsc(gmu); icc_set_bw(gmu->icc_path, 0, 0); icc_set_bw(pwr->icc_path, 0, 0); return; error: Loading Loading @@ -1710,8 +1709,6 @@ static void gmu_remove(struct kgsl_device *device) clear_bit(ADRENO_ACD_CTRL, &adreno_dev->pwrctrl_flag); icc_put(gmu->icc_path); if (gmu->fw_image) { release_firmware(gmu->fw_image); gmu->fw_image = NULL; Loading
drivers/gpu/msm/kgsl_gmu.h +1 −3 Original line number Diff line number Diff line /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef __KGSL_GMU_H #define __KGSL_GMU_H Loading Loading @@ -210,8 +210,6 @@ struct gmu_device { unsigned long kmem_bitmap; const struct gmu_vma_entry *vma; unsigned int log_wptr_retention; /** @icc_path: Interconnect path for the GMU */ struct icc_path *icc_path; }; struct gmu_memdesc *gmu_get_memdesc(struct gmu_device *gmu, Loading