Commit 025c75ba authored Mar 19, 2022 by Konrad Dybcio Committed by Greg Kroah-Hartman Apr 15, 2022

clk: qcom: gcc-msm8994: Fix gpll4 width



[ Upstream commit 71021db1c532c2545ae53b9ee85b37b7154f51d4 ]

The gpll4 postdiv is actually a div4, so make sure that Linux is aware of
this.

This fixes the following error messages:

 mmc1: Card appears overclocked; req 200000000 Hz, actual 343999999 Hz
 mmc1: Card appears overclocked; req 400000000 Hz, actual 687999999 Hz

Fixes: aec89f78 ("clk: qcom: Add support for msm8994 global clock controller")
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20220319174940.341137-1-konrad.dybcio@somainline.org


Tested-by: Petr Vorel <petr.vorel@gmail.com>
Reviewed-by: Petr Vorel <petr.vorel@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

parent f6f1c9a5

drivers/clk/qcom/gcc-msm8994.c

+1 −0

Original line number	Original line	Diff line number	Diff line
	@@ -107,6 +107,7 @@ static struct clk_alpha_pll gpll4_early = {

	static struct clk_alpha_pll_postdiv gpll4 = {		static struct clk_alpha_pll_postdiv gpll4 = {
	.offset = 0x1dc0,		.offset = 0x1dc0,
			.width = 4,
	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],		.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
	.clkr.hw.init = &(struct clk_init_data)		.clkr.hw.init = &(struct clk_init_data)
	{		{