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Commit 0245f11b authored by Chao Hao's avatar Chao Hao Committed by Todd Kjos
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BACKPORT: FROMLIST: iommu/io-pgtable-arm-v7s: Quad lvl1 pgtable for MediaTek 

The standard input iova bits is 32. MediaTek quad the lvl1 pagetable
(4 * lvl1). No change for lvl2 pagetable. Then the iova bits can reach
34bit.

Bug: 167939345
Link: https://lore.kernel.org/patchwork/patch/1301122/


Change-Id: I29095a7f521c73da3fa017e81471ba41db8377ff
Signed-off-by: default avatarYong Wu <yong.wu@mediatek.com>
Signed-off-by: default avatarChao Hao <chao.hao@mediatek.com>
Signed-off-by: default avatarChun-Hung Wu <chun-hung.wu@mediatek.com>
parent fbf0ae52

drivers/iommu/io-pgtable-arm-v7s.c

+9 −3
Original line number Diff line number Diff line
@@ -50,10 +50,16 @@ 
 */

#define ARM_V7S_ADDR_BITS		32

#define _ARM_V7S_LVL_BITS(lvl)		(16 - (lvl) * 4)

/* MediaTek: totally 34bits, 14bits at lvl1 and 8bits at lvl2. */

#define _ARM_V7S_LVL_BITS_MTK(lvl)	(20 - (lvl) * 6)

#define ARM_V7S_LVL_SHIFT(lvl)		(ARM_V7S_ADDR_BITS - (4 + 8 * (lvl)))

#define ARM_V7S_TABLE_SHIFT		10



#define ARM_V7S_PTES_PER_LVL(lvl, cfg)	(1 << _ARM_V7S_LVL_BITS(lvl))

#define ARM_V7S_PTES_PER_LVL(lvl, cfg)	({				\

	!arm_v7s_is_mtk_enabled(cfg) ?					\

	 (1 << _ARM_V7S_LVL_BITS(lvl)) : (1 << _ARM_V7S_LVL_BITS_MTK(lvl));\

})



#define ARM_V7S_TABLE_SIZE(lvl, cfg)					\

	(ARM_V7S_PTES_PER_LVL(lvl, cfg) * sizeof(arm_v7s_iopte))
@@ -63,7 +69,7 @@ 
#define _ARM_V7S_IDX_MASK(lvl, cfg)	(ARM_V7S_PTES_PER_LVL(lvl, cfg) - 1)

#define ARM_V7S_LVL_IDX(addr, lvl, cfg)	({			\

	int _l = lvl;							\

	((u32)(addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \

	((addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \

})



/*
@@ -758,7 +764,7 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, 
{

	struct arm_v7s_io_pgtable *data;



	if (cfg->ias > ARM_V7S_ADDR_BITS)

	if (cfg->ias > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS))

		return NULL;



	if (cfg->oas > (arm_v7s_is_mtk_enabled(cfg) ? 35 : ARM_V7S_ADDR_BITS))