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Commit 02350973 authored by Oak Zeng's avatar Oak Zeng Committed by Alex Deucher
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drm/amdkfd: PM4 packets change to support GWS 



Add a field in map_queues packet to indicate whether
this is a gws control queue. Only one queue per process
can be gws control queue. Change num_gws field in
map_process packet to 7 bits

Signed-off-by: default avatarOak Zeng <Oak.Zeng@amd.com>
Reviewed-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1a058c33

drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c

+1 −0
Original line number Diff line number Diff line
@@ -159,6 +159,7 @@ static int pm_map_queues_v9(struct packet_manager *pm, uint32_t *buffer, 


	packet->bitfields2.engine_sel =

		engine_sel__mes_map_queues__compute_vi;

	packet->bitfields2.gws_control_queue = q->gws ? 1 : 0;

	packet->bitfields2.queue_type =

		queue_type__mes_map_queues__normal_compute_vi;

drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h

+4 −3
Original line number Diff line number Diff line
@@ -176,8 +176,7 @@ struct pm4_mes_map_process { 


	union {

		struct {

			uint32_t num_gws:6;

			uint32_t reserved7:1;

			uint32_t num_gws:7;

			uint32_t sdma_enable:1;

			uint32_t num_oac:4;

			uint32_t reserved8:4;
@@ -272,7 +271,9 @@ struct pm4_mes_map_queues { 
		struct {

			uint32_t reserved1:4;

			enum mes_map_queues_queue_sel_enum queue_sel:2;

			uint32_t reserved2:15;

			uint32_t reserved5:6;

			uint32_t gws_control_queue:1;

			uint32_t reserved2:8;

			enum mes_map_queues_queue_type_enum queue_type:3;

			uint32_t reserved3:2;

			enum mes_map_queues_engine_sel_enum engine_sel:3;